Showing papers on "Carry-lookahead adder published in 2015"

Design of high performance Multiply-Accumulate Computation unit

Abstract: In Digital Signal Processing (DSP), Multiply-Accumulate Computation (MAC) unit plays a very important role and lies in the critical path. Multiplier is one of the most important block in MAC unit. The overall performance of the MAC unit depends on the resources used by the multiplier. Therefore, this paper describes the design of a Partial Product Reduction Block (PPRB) that is used in the implementation of multiplier having better area, delay and power performances. PPRB reduces the partial products row wise by using different multi-bit adder blocks instead of conventional coloumn wise reduction. MAC unit consisting of the multiplier realized using the proposed partial product reduction technique has a delay reduction of 46%, power consumption is reduced by 39% and area requirement is reduced by 17% when compared to MAC unit realised using conventional multiplier architecture.

Performance analysis of 64-bit Carry Lookahead Adders using conventional and hierarchical structure styles

Abstract: This paper introduces performance analysis of 64-bit Carry Lookahead Adders using conventional and hierarchical structure styles. We evaluate conventional carry lookahead adder (CLA) and hierarchical carry lookahead adder (HCLA) using different parameters. Our design is targeted into FPGA Virtex 7 family. Area, delay, and area-delay product of all design choices are reported. In the experimental results, we reduced CLA delay and area using radix-2 which performed better than traditionally used radix-4 CLA. In addition, we showed that CLA using conventional structure has better performance than the hierarchical structure.

Leakage power reduction in MTCMOS based high speed adders

Abstract: Power and area remain the main constraint in designing of VLSI circuits. Also, adder being one of the main components of processor design is highly researched digital module. In this paper high speed adders are designed using 130nm CMOS process and are being evaluated for their performance at lower technologies. The power dissipation, delay and area are compared for Carry select adder, ripple carry adder and carry look ahead adders. Simulation tools available in Mentor Graphics HEP II package has been used for designing, simulation and for post simulation analysis. It is shown that although the power dissipation and area overhead are high for the carry lookahead adder, the delay is minimum as compared to the other two adders and hence can be used in high speed digital modules. Further it was also shown that by using MTCMOS based design techniques the leakage power can be drastically reduced.

Pipelined Two-Operand Modular Adders

Abstract: Pipelined two-operand modular adder (TOMA) is one of basic components used in digital signal process- ing (DSP) systems that use the residue number system (RNS). Such modular adders are used in binary/residue and residue/binary converters, residue multipliers and scalers as well as within residue processing channels. The structure of pipelined TOMAs is usually obtained by in- serting an appropriate number of pipeline register layers within a nonpipelined TOMA structure. Hence the area of pipelined TOMAs is determined by the nonpipelined TOMA structure and by the total number of pipeline registers. In this paper we propose a new pipelined TOMA, that has a considerably smaller area and the attainable pipelining frequency comparable with other known pipelined TOMA structures. We perform comparisons of the area and pipe- lining frequency with TOMAs based on ripple carry adder (RCA), Hiasat TOMA and parallel-prefix adder (PPA) using the data from the very large scale of integration (VLSI) standard cell library. n m m m X X X with i m i x Z  . This mapping is the bijection and for X, Y  ZM and for i m i i y x Z  , , we have i m i i i y x z   ,where  denotes addition, subtraction or