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Design Of Analog Cmos Integrated Circuits

Approximate computing has emerged as a new paradigm for high-performance and energy-efficient design of circuits and systems. For the many approximate arithmetic circuits proposed, it has become critical to understand a design or approximation technique for a specific application to improve performance and energy efficiency with a minimal loss in accuracy. This article aims to provide a comprehensive survey and a comparative evaluation of recently developed approximate arithmetic circuits under different design constraints. Specifically, approximate adders, multipliers, and dividers are synthesized and characterized under optimizations for performance and area. The error and circuit characteristics are then generalized for different classes of designs. The applications of these circuits in image processing and deep neural networks indicate that the circuits with lower error rates or error biases perform better in simple computations, such as the sum of products, whereas more complex accumulative computations that involve multiple matrix multiplications and convolutions are vulnerable to single-sided errors that lead to a large error bias in the computed result. Such complex computations are more sensitive to errors in addition than those in multiplication, so a larger approximation can be tolerated in multipliers than in adders. The use of approximate arithmetic circuits can improve the quality of image processing and deep learning in addition to the benefits in performance and power consumption for these applications.

Approximate Arithmetic Circuits: A Survey, Characterization, and Recent Applications

Formation of abrupt tunneling junction for the sub-nanometer tunnel FET (TFET) is crucial for achieving better electrical behavior. This task is more challenging in the case of dopingless TFETs (DL TFETs). In this concern, we propose a novel design of DL TFET, wherein a metallic layer has been placed in the oxide region at the space present between gate and source electrode (used for inducing p+ region) of conventional dopingless n-TFET to overcome the issue of low on-state current ( $\text{I}_{\mathrm{on}}$ ) due to presence of tunneling barrier. Proposed modification is helpful for achieving steeper tunneling junction at the source/channel interface, which enables higher tunneling generation rate of charge carriers at this interface. The optimization for work function of the metal layer (ML) has been performed for improving $\text {I}_{\mathrm{on}}$ , point subthreshold swing and threshold voltage ( $\text {V}_{\text {th}}$ ). Finally, the impact of the ML misalignment from the gate/source terminal and optimization of its length is also presented.

A New Design Approach of Dopingless Tunnel FET for Enhancement of Device Characteristics

To suppress the ambipolar behavior and improve RF performance in tunnel field-effect transistors (TFETs), a Z-shaped (ZS)-TFET is proposed. The proposed ZS-TFET is more scalable than other vertical band-to-band-based TFETs and provides higher ON-state current ( ${I} _{ {\mathrm{\scriptscriptstyle ON}}}$ ), larger ON/OFF current ratio ( ${I} _{ {\mathrm{\scriptscriptstyle ON}}}/{I} _{ {\mathrm{\scriptscriptstyle OFF}}}$ ) and lower subthreshold swing compared to conventional TFETs. These advantages stem from the tunneling junction in the ZS-TFET being perpendicular to the channel direction, which facilitates the formation of a relatively large tunneling junction area. The ZS body makes use of both vertical and horizontal fields while suppressing the lateral parasitic tunneling current. In addition, by using a ZS gate in the proposed device, the energy band diagram near the source is modulated to create an N+ source pocket which creates a downward band bending of the potential, similar to PNPN-like structures. Finally, the proposed structure significantly improves the analog/RF figure-of-merit.

A Novel PNPN-Like Z-Shaped Tunnel Field- Effect Transistor With Improved Ambipolar Behavior and RF Performance

In this paper, for the first time, an InAs/Si heterojunction double-gate tunnel FET (H-DGTFET) has been analyzed for low-power high-frequency applications. For this purpose, the suitability of the device for low-power applications is investigated by extracting the threshold voltage of the device using a transconductance change method and a constant current method. Furthermore, the effects of uniform and Gaussian drain doping profile on dc characteristics and analog/RF performances are investigated for different channel lengths. A highly doped layer is placed in the channel near the source–channel junction, and this decreases the width of the depletion region, which improves the ON-current ( ${I_{\rm{\scriptscriptstyle ON}}}$ ) and the RF performance. Furthermore, the circuit-level performance assessment is done by implementing a common source amplifier using the H-DGTFET; a 3-dB roll-off frequency of 230.11 GHz and a unity-gain frequency of 5.4 THz were achieved.

Performance Enhancement of Novel InAs/Si Hetero Double-Gate Tunnel FET Using Gaussian Doping

Reliability is a significant strategy concern for modern day multi core embedded systems. On chip communicating systems are vulnerable to permanent network faults and transient faults which might essentially affect the performance of the system. Targeting at fault tolerance solution for cores with faults in Network on Chip (NoC), this paper proposes an energy efficient fault tolerant NoC architecture using spare core. The proposed strategy comprises of finding smallest rectangular region to place the given application using a heuristic technique, and mapping vertices within the selected region, and selecting a region which results maximum overall performance and minimum communication energy. Spare core is placed within a region and connected to the vertices. Many application core graphs are used to evaluate the proposed technique. The simulation outcomes of many fault injection tests indicate that the proposed technique results in performance enhancement while also saving communication energy.

A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core

Approximate computing has received significant attention as an attractive paradigm for error-tolerant applications to reduce the power consumption, delay and area with some trade-off in accuracy. This paper proposes the design of a novel approximate 4–2 compressor. A modified architecture of Dadda Multiplier is presented for the effective utilization of the proposed compressor and to reduce the error at the output. Through extensive experimental evaluation, the efficiency of the proposed compressor and multiplier are evaluated in a 45 nm standard CMOS technology and their parameters are compared with those of the state-of-the-art approximate multipliers. The results show that the proposed compressor accomplish a significant reduction in error rate compared to other approximate compressors available in the literature. In addition, the proposed multiplier shows 35%, 36% and 17% reduction in power consumption, delay and area respectively compared to those of exact multiplier. The effectiveness of multiplier is assessed by some of the image processing applications. On an average, the proposed multiplier processes images with 85% structural similarity compared to the exact output image.

Design and analysis of multiplier using approximate 4-2 compressor

In multi-processor system on-chip, each processor produces and consumes high data. Hence, transporting of data becomes crucial in MPSOC. Therefore, Network on Chip (NoC) is preferred as an alternate medium because it provides good communication performance with comprehensive fast operation. This paper proposes the placement of spare core and its communication energy constraints while considering temporary and permanent fault occurrences in the core. We investigated energy metrics instead of spare core, bringing up lots of saving in terms of communication energy over the previous algorithms.

Communication energy constrained spare core on NoC

In this paper, the problem of spare core position when faults occur at core on Network on Chip (NoC) is proposed. More precisely, a fine grained spare core position is proposed, which goes for enhancing the entire system performance and communication energy consumption, while considering the occurrence of permanent, transient and intermittent faults in the system. This method finds the spare core near to perilous cores, as the key hypothetical involvement, the problem of spare core placement and its impact on system is discussed.

M H Vasantha

Papers

Performance Enhancement of Novel InAs/Si Hetero Double-Gate Tunnel FET Using Gaussian Doping

A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core

Design and analysis of multiplier using approximate 4-2 compressor

Communication energy constrained spare core on NoC

A fine grained position for modular core on NoC