Showing papers on "Channel length modulation published in 1976"

Method for fabricating diffusion self-aligned short channel MOS device

Abstract: A diffusion self-aligned, short channel device may be fabricated by ion implantation of an n-type channel region within a p-type substrate. A p-type dopant is then implanted in and driven through a portion of the n-type channel region to form an impurity region. A diffusion self-aligned n-type channel region is then disposed in the p-type impurity region and in the n-type channel region. The method allows for the simultaneous fabrication of a channel implanted MOSFET as well as a standard MOSFET. The resulting diffusion self-aligned, short channel device is a high gain, high speed small device which can be simply combined and fabricated with channel-implanted depletion devices and low body effect devices in an integrated circuit.

A high power MOSFET with a vertical drain electrode and a meshed gate structure

Abstract: A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel width per unit area. The p-channel device with an offset gate structure was fabricated from an n on p/SUP +/ epitaxial wafer by using polysilicon gate and ion implantation processes. The device can be operated stably at ambient temperatures up to 180/spl deg/C. While the bipolar transistor is a suitable power device in the low voltage region, the MOSFET looks more promising in the high voltage region than the V-FET and the bipolar transistor.