Showing papers on "Circuit diagram published in 1989"

System and method of generating a source program from inputted schematic information

Abstract: According to the present invention, using a display terminal for conversation, a module structure diagram (schemata expressive of the connectional relations among respective program modules) is created, and a processing flow diagram (a kind of processing flow chart), an internal data definition diagram (schemata for specifying the formats etc. of data for use in processes) and an interface data definition diagram (schemata for specifying the formats etc. of arguments, common data between the modules, etc.) are created for each module, the created contents being stored in a memory. Further, the schematic information items of the module structure diagram, processing flow diagram, internal data definition diagram and interface data definition diagram are read out from the memory for each module and have stereotyped sentences and symbols added thereto, to generate the individual sentences of a source program. These sentences are edited according to the rules of a language, to complete the source program. If necessary, the various diagrams are printed out and utilized as program specifications.

Arrangement for protecting passengers in vehicles

Abstract: The invention relates to an arrangement for protecting passengers for vehicles in which the information which is present for example in an anti-lock system is evaluated in an enabling processor for enabling the safety measures for the protection of the passengers. An exemplary embodiment is described and is shown in a block circuit diagram.

Semiconductor integrated circuit device having improved input/output interface circuit

Abstract: A semiconductor integrated circuit device includes an external terminal (17, 140), an internal logic circuit (110), and an input/output interface circuit (120, 130). The input/output interface circuit includes an input circuit (7), a selection circuit (10) and an output circuit (8). The input circuit (7) receives an input signal and supplies the internal logic circuit (110) with the same. The selection circuit (10) selects either the input signal supplied from the input circuit (7) or an output signal supplied from the internal logic circuit (110). The output circuit (8) outputs the selected one of the input signal and output signal to the external terminal. A loop circuit is formed by the input circuit (7), selection circuit (10) and output circuit (8). The loop circuit logically includes an odd number of inverters.

Method for deleting unused gates and method for manufacturing master-slice semiconductor integrated circuit device using the deleting method

Abstract: A method is provided for manufacturing a master slice semiconductor integrated circuit device. Initially, a first total circuit diagram which is to be reformed into a master slice semiconductor integrated circuit device is defined. First and second circuit points on the first total circuit block which are to be used respectively as input and output terminals of the master slice semiconductor integrated circuit device are specified. Next, signal transmitting paths are successively traced from the output to the input of each logic gate located in the signal transmitting paths in actual use. In the course of the tracing, these traced gates are marked and the logic gates actually in use are identified. As a result, in addition to those logic gates having unused output terminals, the gates constituting a closed loop isolated from the signal transmitting paths for transmitting substantial output signals are identified as unnecessary gates and deleted. Further, gates outputting only a fixed value are determined and designated unnecessary gates which are also deleted.

Integrated circuit placement method using netlist and predetermined ordering constraints to produce a human readable integrated circuit schematic diagram

Abstract: A method is disclosed for determining the placement of circuit elements in an integrated circuit where the circuit elements are initially represented by a netlist. The method preferably includes the steps of providing predetermined ordering constraints that indicate the preferred relative locations of the circuit elements that are represented in the netlist, partitioning the circuit elements from the netlist in accordance with a predetermined balancing criterion; determining the value of a cost function associated with the partitioning steps, and selecting a particular partition based upon the value of the cost function.

An optimal transistor-chaining algorithm for CMOS cell layout

Abstract: A fast algorithm is produced for the optimal transistor chaining problem in CMOS functional cell layout based on T. Uehara and W.M. van Cleemput's layout style (IEEE Trans. Comput., vol. C-30, p.305-12, May 1981). The algorithm takes a transistor-level circuit schematic and outputs a minimum set of chains. Possible diffusion abutments between the transistor pairs are modeled as a bipartite graph. A depth-first search algorithm is used to search for the optimal chaining. Theorems on the number of branches needed to be explored at each node of the search tree are derived. A theoretical lower bound on the size of the chain set is derived. This bound enables pruning the search tree efficiently. The algorithm has been implemented and tested. It is able to find optimal solutions almost instantly for all the cases available to use from the literature. >

A 36 kb/2 ns RAM with 1 kG/100 ps logic gate array

Abstract: An LSI device incorporating a 36-kb RAM and a 1k-gate logic array and using a 0.8- mu m sidewall base contact structure (SICOS) transistor process and four-layer metallization, is described. RAM and peripheral logic have been included in one chip to reduce input/output delay and interconnection delay between the RAM and logic. The chip layout is shown together with the circuit schematic of the RAM macro. RAM address access waveforms are shown along with the waveform of a 21-stage ring oscillator. Major device characteristics are summarized. >

On CMOS exclusive OR design

Abstract: A collection of eight different CMOS EXOR (exclusive OR) gates is presented. The circuit implementations of these EXOR gates range from three to a dozen transistors. A circuit diagram, layout size, and simulation results from LSIM, SPICE, and IRSIM are given for each of the circuits. >

From network to artwork : automatic schematic diagram generation

Abstract: During the automatic generation of complex VLSI-circuits from a high level description it is necessary to provide some graphical feedback to the designer. This can be done by drawing a schematic diagram of a temporarily constructed network. To overcome the time consuming manual drawing of such diagrams, an automatic schematic diagram generator is developed. The generator is composed out of a placement and a routing part. For both parts user oriented algorithms based on some guidelines traditionally followed in manual drawing of schematic diagrams are constructed. The algorithms are implemented and results are shown. Koster, GJ.P. and L. Stok FROM NETWORK TO ARTWORK: Automatic Schematic Diagram Generation. Faculty of Electrical Engineering, Eindhoven University of Technology, 1989. EUT Report 89-E-2l9 The address of the authors is: Design Automation Section Faculty of Electrical Engineering Eindhoven University of Technology P.O. Box 513 5600 MB Eindhoven The Netherlands Tel. (040).473373 Email: leon@euteal

The ringer: an efficient, high repetition rate circuit for electromagnetic launchers

Abstract: The Meatgrinder is an efficient, current-multiplying circuit which can be used to optimize the energy transfer to various electromagnetic gun configurations. The authors present a simple variant of the Meatgrinder circuit which permits a first-order current profiling into the gun and recovery of the inductive energy in the barrel at a high repetition rate. The circuit is basically a one-stage Meatgrinder which utilizes the ringing of the energy storage capacitor (less than 40% reversal) to perform the opening switch function and a solid-state diode as the crowbar switch between the two mutually coupled inductors. With resonant charging, this results in a completely passive, high-repetition-rate electromagnetic-gun power supply. Since most of the barrel energy is recovered, a railgun with negligible muzzle flash can be realized. >

CMOS inter-chip interconnection circuit using high-T/sub c/ superconducting tunnel junctions and interconnections

Abstract: The analysis of a possible low-voltage CMOS interconnection circuit utilizing high-T/sub c/ superconducting tunnel junctions (TJs) and interconnections for very-high-speed interchip communication at low temperatures (4-77 K) is presented. The circuit uses tunnel junctions as diodes to clip voltage swings between well-controlled levels defined by the energy gaps of the high-T/sub c/ materials. The circuit dissipates five to eight times less power than conventional designs, produces very small current transients, and has good immunity to noise from input voltage fluctuations, crosstalk, and simultaneous switching of drivers. >

Digital circuit on x=0.35 Hg/sub 1-x/Cd/sub x/Te

Abstract: The letter reports the demonstration of a digital circuit on HgCdTe. The circuit is a single-bit dynamic shift register, using a ratioless inverter design. The circuit was fabricated on epitaxially grown HgCdTe, with a cutoff wavelength of 3.56 μm at 77 K. The circuit's properties are presented and discussed.

A 2.5 kW cascaded Schwarz converter for 20 kHz power distribution

Abstract: Because it avoids the high currents in a parallel loaded capacitor, the cascaded Schwarz power converter should offer better component utilization than converters with sinusoidal output voltages. The circuit is relatively easy to protect, and it provides a predictable trapezoidal voltage waveform that should be satisfactory for 20 kHz distribution systems. Analysis of the system is enhanced by plotting curves of normalized variables vs. gamma /sub 1/, where gamma /sub 1/ is proportional to the variable frequency of the first stage. Light-load operation is greatly improved by the addition of a power recycling rectifier bridge that is back biased at medium to heavy loads. Operation has been verified on a 2.5 kW circuit that uses input and output voltages in the same range as those anticipated for certain future spacecraft power systems. >

Lsi trouble analyzing device

Abstract: PURPOSE:To obtain a trouble analytic result without any operator's intervention by comparing a simulation result with an actual device measurement result, detecting a fault position, etc., of a device according to the comparison result, and identifying a part corresponding to the fault position. CONSTITUTION:An actual device measurement part 5 inputs a test pattern 2 to a LSI device 1 and measures its output. A fault simulation part 6 simulates the fault states of respective elements of the device according to circuit constitution data 3, measures output patterns of the respective fault states for the input pattern 2, and stores the result as a fault simulation result 9. A logic pattern comparing and testing part 7 generates a correspondence table 10 showing which part in a layout structure diagram respective parts of the circuit diagram of the LSI correspond to according to the data 3 and layout structure data 4. A fault display device 20 has a LSI fault analytic part 11 and a display 12 and the circuit diagram and layout structure diagram of the LSI are displayed on the display 12 while the parts corresponding to LSI fault positions in the diagrams are marked.

Circuit differential extracting device

Abstract: PURPOSE:To automatically extract differential information between new and old circuits by extracting the difference of connection states between new and old circuit diagram information and preserving the extracted difference as a circuit change history so that the occurrence of a visual mistakes and the increase of working manhours can be avoided. CONSTITUTION:The new/old circuit diagram information inputted from an input device 1 is temporarily stored in a data memory 3. Corrected old connection information and the latest corrected one are extracted and the fan-out sources of the new and old connection are decided for each series. These decided fan-out sources are used as keys for comparison between the new and old connection information. Then the addition or deletion of connection series are decided by the presence or absence of both fan-out sources. At the same time, the connection change is decided within a connection series according to the change of the connection state to the fan-in side. Thus the differential information is decided and preserved in a circuit change history generating means 6 as a circuit change history together with the new circuit diagram information.

Board for printed circuits with transistors, especially for laboratory applications.

Abstract: The invention relates to a universal conductor track structure for printed circuits, on which various standard and special circuits can be implemented with standardised components of various types (resistors, capacitors, trimmers, microswitches and at least one transistor). At the same time, this universal structure is intended to be used as a completely fitted standard printed-circuit board with a modular character. In this way, it is possible for both the professional and the amateur electronics technician to produce a completely fitted board in a few minutes, just from the circuit diagram. The logical arrangement of the conductor track layout is determined in essence: 1) By the transistor output field located in the centre, from which each main track (1-6) is reached without problem by the planned transistor. 2) That the main tracks (1 - 4) can be mutually accessed, in the minimum case, at double the grid spacing. 3) That the main tracks are laid parallel to one another, in stepped layered form, from the centre outwards in order to allow all the main tracks to be connected to one another, without jumpers, using components of different grids. 4) By the capability to hold trimmers, which requires an additional angular form of the tracks. 5) By the modular character which allows interlocking of the tracks with a plurality of basic boards arranged in rows.

Circuit diagram cad device

Abstract: PURPOSE:To easily confirm the connection state between signal lines covering plural pages with a circuit diagram CAD device by plotting and displaying the relation among a signal line covering plural pages, an unconnected signal line and each page. CONSTITUTION:An inter-page connection data origination part and a cross- reference adding part originates inter-page connection data by an instruction given from an input part and based on the circuit data stored in a circuit data memory part and store this data in a memory part. Then an inter-page connection display data origination part reads out the inter-page connection data in response to the input and originates the inter-page connection display data as shown in a diagram in accordance with the unconnected state and the connected state of the output only, etc., to display the originated data at a display part. Thus it is possible to visually confirm the inter-page connection state and to improve the production efficiency of a logic circuit.

A CAD tool for circuit diagram extraction from VLSI layout cells

Abstract: The design and development of a software tool for verifying VLSI design in a layout format are presented. This tool displays the circuit diagram relative to a layout that is extracted from the layout definition file. This software tool is implemented in the C-language on the Microvax GPX/II workstation and is based on the MAGIC layout editing system. >

Method and apparatus for preparing measurement specifications of electronic circuits

Abstract: A method for preparing the measurement specifications of an electronic circuit comprises the steps of preparing testing peripheral circuit diagrams for individual measurement items by adding standardized testing peripheral circuit modules to the basic peripheral circuit diagram of the electronic circuit, preparing an overall testing peripheral circuit diagram for use in making measurements corresponding to all the measurement items by synthesizing these testing peripheral circuit diagrams with one another, and preparing measurement specifications for individual measurement items for use in making measurements employing the overall testing peripheral circuit diagram, from the overall testing peripheral circuit diagram and the testing peripheral circuit diagrams. An apparatus for carrying out such a method has an input device, a data base, a section for preparing testing peripheral circuit diagrams for individual measurement items, a section for preparing an overall testing peripheral circuit diagram by synthesization, a section for preparing measurement specifications for individual measurement items, and an output device for outputting the measurement specifications thus prepared.

Method for power distribution between a plurality of parallel-connected servo drive amplifier ballast circuits, and a ballast circuit operating in accordance with this method

Abstract: The invention relates to a method for power distribution between a plurality of parallel-connected servo drive amplifier ballast circuits, and to a ballast circuit for servo drive amplifiers having a ballast resistor (5), which can be connected to the electrical power supply lines (8) of the servo amplifier (6) and can be pulsed by means of a switching device (3, 4), and having a fixed switching device response threshold (2) for limiting the intermediate-circuit DC voltage on an energy-storage capacitor (9) which is connected in parallel with the servo amplifier (6). The associated drawing shows an outline circuit diagram of such a ballast circuit. The invention is based on the object of creating a capability to operate a plurality of such ballast circuits from a common DC voltage busbar, irrespective of the number of shafts supplied. To this end, in the case of the ballast circuit according to the invention, the fixed switching device response threshold (2) of (each of) the ballast circuit(s) is increased by a voltage amount (UC), by means of a match circuit (1) whenever the ballast resistor (5) is pulsed, and is reduced again in the event of a load, with said voltage amount (UC) being dimensioned such that it produces compensation for the component tolerances of the fixed thresholds (2) of parallel-operated ballast circuits during the load duration, which is normal in servo operation, of the ballast circuit.

Matching a UPS to the computer market

Abstract: The authors describe the expectations a computer user should have of his UPS (uninterruptible power supply) system, and how these expectations are satisfied in the new Siemens B41 model. The computer load characteristics are discussed, and a list of essential and 'good to have' characteristics is presented. The new model is presented with main circuit diagram, description of the control electronics, and mechanical design. Voltage and current waveforms are also shown. >

Circuit input supporting device for cad system

Abstract: PURPOSE:To easily and exactly execute an input of circuit information to a CAD system by generating a prototype text in accordance with executing function information and pin constituting information, and arrangement position information of a designated circuit cell. CONSTITUTION:By pointing an area on a guide screen 21 by a pointer means 23, an arrangement position of a circuit cell of a circuit diagram 10 is designated, and also, classifying information of each circuit cell is designated. A prototype text generating means 50 refers to circuit cell information 41 and derives executing function information and pin constituting information which a designated circuit cell classification of a designated classification discriminating means 30 has, and also, generates automatically a prototype text 60 in accordance with the executing function information and the pin constituting information which have been derived, and the arrangement position information of the circuit cell which has been designated by the pointer means 23. In such a way, an input of circuit information can be executed simply and exactly.

A CAD tool for circuit extraction from VLSI layout cells

Abstract: The authors present an approach to converting and displaying a VLSI layout definition file, such as one produced by the MAGIC layout editing system, into a circuit diagram. The ideas presented have been incorporated into a software tool written in C language for the Microvax GPX/II workstation; the routines in the graphic kernel system are used for the graphics component of the software. An example of a cell layout developed using MAGIC is shown along with the MAGIC layout definition file relative to this. It is also demonstrated that the circuit diagram developed by such a CAD (computer-aided design) tool can be useful in verification of layout. The terminal interconnectivity information generated from the layout definition file can also be used directly for circuit simulation. >

Crt operating device

Abstract: PURPOSE:To rapidly perform a counterpart operation without observing a document such as a drawing, etc., by displaying information not only of the name of a plant equipment in which abnormality is generated but for the response of an operator. CONSTITUTION:A table 2f to store a plant equipment layout drawing as picture data, and a table 2g to store a circuit diagram for every plant equipment and a conditional logic diagram for an operation, etc., as a graphic picture are provided, and those data re synthesized with a process quantity inputted from a plant, then, displayed. Therefore, the information of a desired plant equipment can be obtained on CRT display always used in a plant operation. In such a way, it is possible to improve the response of the operator at the time of generating the abnormality in the plant equipment, and to perform the operation based on the information obtained from the CRT display without observing the document such as a specific drawing, etc.

Apparatus for displaying simulation result

Abstract: A result of simulation for an object circuit is displayed as a circuit diagram in which respective elements in the object circuit are colored according to the simulation result so that the simulation result can be easily understood. The elements displayed in colors include not only active and passive elements but also signal lines interconnecting them and the branches of the signal lines, so that the result of the simulation can be displayed in detail in color.

Active frequency diplexer

Abstract: The invention is based on the object of developing known active frequency diplexers further in such a manner that an amplifer for a higher frequency range with as large a series capacitance as possible can be coupled in without this resulting in greater impairment for the frequencies of a lower frequency range. Furthermore, large-signal distortions which are produced by simultaneous contribution of signals from the lower and upper frequency ranges should be negligibly small. In addition, the circuit complexity required for implementing the active frequency diplexer should be as little as possible. The solution of the present object consists in that the base point of the antenna (A) is connected to the input of the FM amplifier (V1) by a series circuit of three capacitors (C1, C2, C3). In addition, the base point is connected to the gate electrode (G) of a field-effect transistor (FET) by the first capacitor (C1) and a first inductance (L1) connected in series therewith. Finally, the base point is also connected to the source electrode (S) of the field-effect transistor via the first and second capacitors (C1, C2) and a second inductance (L2) connected in series therewith and to the input of the LMS amplifier (V2) and via a resistor (R2) to earth. A preferred field of application for the active frequency diplexer according to the invention are active antennas for motor vehicles. The drawing shows a circuit diagram of the... Original abstract incomplete.

Lattice point setting system for digitizer

Abstract: PURPOSE:To realize the digitized input over an entire circuit diagram by setting a gritting point accordant with the characteristics of a circuit parts in a peripheral area of this parts in a digitizer and at the same time setting the rough gritting points matching with the distances among standardized pins occupying the greater number of circuit parts in the non-peripheral areas respectively. CONSTITUTION:The coordinate positions of the circuit parts used in an input circuit diagram 20 are designated by a cursor 11. The lattice points in the peripheral areas of those coordinate positions are replaced with those lattice points stored in a lattice point information storing means 13. Then the lattice points proper to the circuit parts stored in a parts lattice point information storing means 15 are set. Thus it is possible to set an accurate pattern in a peripheral area of the circuit parts and also to set the rough lattice points in the non-peripheral areas of the circuit parts respectively. Then the digitization is possible without increasing the quantity of data.

Reverse engineering as a framework for design verification

Abstract: A new framework is described for layout design verification The main idea is to extract the netlist from the layout and regenerate the schematic database from this netlist The usefulness of such a database is described An algorithm for generating the switch-level schematic diagrams is given It is superior to previous tools in that it is deterministic (other works use heuristics and therefore cannot handle certain problems), it is fast (others are up to 100 times slower), it is technology independent (others were written for CMOS only), and it can be implemented in an extremely short program (around 1000 lines of C) >