Showing papers on "Circuit diagram published in 1997"

System and method for generating effective layout constraints for a circuit design or the like

Abstract: A computer system and computer implemented method for deriving constraints with which to direct automatic integrated circuit layout is disclosed. The present invention is particularly adapted for use in the design of large integrated circuits with complex synchronous timing behavior. Preferably, the invented computer system includes means for storing a netlist data structure within a storage means is provided, the netlist data structure representing a circuit configuration having a plurality of circuit elements and representing static timing information for the circuit configuration; means for selecting specified circuit elements to be used for generating the layout constraints, whereby the specified circuit elements that are selected are fewer than, i.e. represent a proper subset of, the plurality of circuit elements of the circuit configuration; means for identifying a most critical path through each of the specified circuit elements based upon the static timing information, whereby preferably the most critical path is that path having the least slack defined as the difference between a required time at which a signal should reach the specified circuit element and an arrival time at which the signal is expected to reach the specified circuit element; and means for generating layout constraints from the most critical path through each of the specified circuit elements, whereby at least one constraint is generated covering each of the specified circuit elements. Also disclosed is a feature whereby any paths that do no meet specified filter criteria, and paths that are duplicates of others, are discarded, thereby retaining only irredudant critical paths on which to base layout constraints.

Record and play: a structural fixed point iteration for sequential circuit verification

Abstract: This paper proposes a technique for sequential logic equivalence checking by a structural fixed point iteration. Verification is performed by expanding the circuit into an iterative circuit array and by proving equivalence of each time frame by well-known combinational verification techniques. These exploit structural similarity between designs by local circuit transformations. Starting from the initial state, for each time frame the performed circuit transformations are stored (recorded) in an instruction queue. In subsequent time frames the instruction queue is re-used (played) and updated when necessary. At some point the instruction queue does not need to be modified any more and is valid in all subsequent time frames. Thus, a fixed point is reached and machine equivalence is proved by induction. Experimental results show the great promise of this approach to verify circuits after resynthesis and retiming.

Semiconductor substrate having alignment marks for locating circuitry on the substrate

Abstract: An integrated circuit device having alignment marks that are located on the integrated circuit device semiconductor substrate and aligned to the integrated circuit. The alignment marks are used in conjunction with a circuit diagram of the integrated circuit to determine the point on the bottom of the semiconductor substrate residing beneath the portion of the integrated circuit which the practitioner desires to access.

Standard cell power-on-reset circuit

Abstract: A method of designing a reset circuit for a digital integrated circuit (IC) layout is described. The reset circuit is designed with the intention of making it visually non-detectable in the digital IC layout by implementing the reset circuit entirely in digital elements and then using standardized digital layout cells and routing such that the reset circuit is essentially non-discernible from the digital circuitry of the IC device layout. In addition, circuit elements are designed using devices having dimensions that are essentially the same as typical digital devices in the digital IC layout.

Apparatus for optimization of circuit design

Abstract: An apparatus for optimization of circuit design such as integrated circuits and printed circuits and an optimization process of the initial layout circuit, from results of the initial layout of the circuits, circuit connection informations after layout, cell positions, and interconnection routing, capacitance and resistance of interconnections are fetched. Optimization is made by local modification to the circuit such as cell placement and buffer insertion in consideration of keeping cell placements and interconnection routing so as to reduce delay, power consumption and circuit scale. Layout information to be changed by the local modification to the circuit is accurately recalculated on the basis of the original layout information. Renewed circuit connection information and newly calculated layout information are transmitted as restriction requirements to the layout section for conducting the relayout.

Semiconductor device and circuit constitution method thereof

Abstract: PROBLEM TO BE SOLVED: To provide a circuit constitution method for a semiconductor device of high performance in which a hardware is changed for each operation specification in optimum manner. SOLUTION: Using a control data flow graph S21 prepared from an operational describe, a data path circuit part 20A, corresponding to an initial circuit in higher order composition where a logical circuit is composed with the initial circuit as a nucleus, and a control circuit part 30 for controlling an operation of the data path circuit part 20A prepare a semiconductor device constituted with a reconfigurable circuit which can vary a circuit constitution. Based on circuit data as a result of the higher order composition, data path wire connection information as wire connection information of the data path circuit part 20A and control information for controlling the operation of the data path circuit part are generated, and the data path wire connection information and the control information is mapped on the reconfigurable circuit, and the data path circuit part 20A and the control circuit part 30 are circuit-constituted according to mapping information. COPYRIGHT: (C)1998,JPO

Bisramgen: a silicon complier for built-in self-repairable random-access memories

Abstract: This research focuses on a CAD tool, BISRAMGEN, that synthesizes layout geometries of built-in self-testable and built-in self-repairable single-port static and dynamic RAM modules with flexible, user-specified geometry parameters and CMOS design rules. Such a tool is of great importance in commercial microelectronics industry because it allows CAD designers to generate fault-tolerant RAM layouts very efficiently. Built-in self-repair (BISR) is an extremely cost-effective technique to enhance the manufacturing yield and field survivability of state-of-the-art integrated circuits employing deep submicron CMOS fabrication technology. BISR circuits not only increase the manufacturing yield and fault-tolerance of RAMs, but also allow them to be used in mission-critical field applications where diagnosing faults and performing replacements are too costly or impossible (such as space, avionic and oceanic applications). Furthermore, hard failures in embedded RAMs used in high-density microprocessors and ASICs cannot be repaired by other means due to the difficulty of accessing the internal nodes of the circuit. Currently, the task of incorporating such circuitry within embedded memories can be performed only manually or using semi-custom design techniques by the designer, and is thereby a major bottleneck in the design cycle. BISRAMGEN takes only about 10 minutes of CPU time on a DEC 3100 to build a 1 Mb static RAM array with 8 spare rows and the BIST/BISR circuitry. BISRAMGEN takes as input a high-level specification of the RAM parameters and the CMOS geometrical design rules, and builds an efficient built-in self-repairable RAM layout that is both drc and lvs-correct for the given ruleset (i.e., the layout satisfies the design rules for the chosen process and topologically agrees with the circuit schematic). BISRAMGEN uses a novel BIST approach based on the Inductive Fault Analysis (IFA) technique which guarantees a high physical defect coverage for CMOS RAMs. BISRAMGEN is design-rule independent; it can be used with a wide range of submicron CMOS processes developed by commercial microelectronics companies. It has been tested for processes supporting at least three layers of metal, with $\lambda$, the minimum feature size, ranging from 0.5 $\mu$m to 2.0 $\mu$m, and found to produce correct and efficient layouts. BISRAMGEN achieves a modest area overhead (typically less than 7%) for BIST, BISR and redundant elements combined, for a range of 10 representative CMOS processes with $\lambda$ varying from 0.5 $\mu$m to 2.0 $\mu$m. The area overhead achieved by BISRAMGEN is found to be comparable with or better than published results obtained using full-custom layout design. BISRAMGEN achieves a high yield of more than 95% with 10 spot defects scattered in the layout and a reliability of above 96% through 2 years of chip use. Furthermore, BISRAMGEN uses an innovative circuit technique for BISR (US patent pending) that guarantees effective zero delay overhead on RAM access time during normal operation. Existing BIST and BISR techniques are either associated with delay overhead (9) or use expensive circuit techniques that cause extra processing steps or more area overhead (54). (Abstract shortened by UMI.)

Method for spawning two independent states in a state flow diagram

Abstract: A system and method for entering a circuit design into a computer using a schematic capture package. The schematic capture package is modified to include a library of state flow components represented by symbols which can be connected to produce a desired representation of the circuit design. The system allows a circuit design to be displayed on a video terminal using both state flow diagram and the schematic diagram symbols, with terminals of the state flow symbols connecting to terminals of the schematic symbols. The state flow diagram using state flow symbols is combined with a schematic diagram including schematic symbols to generate a netlist representing the combined circuit.

Delaying time calculating method and logical simulation device

Abstract: PROBLEM TO BE SOLVED: To improve the operation frequency of a logical circuit by optimizing the propagation delaying time of a cell for every cell. SOLUTION: After a circuit diagram reading part 11 reads a circuit diagram, a cell selection part 12 selects a cell to calculate a delaying time. A cell kind judging part 13 judges the kind of the cell selected by the selection part 12, and an error reading part 14 reads the maximum error of the delaying time corresponding to the kind of the selected cell from a delay library 10. A delaying time calculation part 15 calculates the prescribed delaying time of the selected cell. A maximum/minimum calculation part 16 calculate a maximum delaying time by multiplying the prescribed delaying time calculated by the calculation part 15 and the maximum error read from the delay library 10 by the reading part 14. A simulation executing part 17 executes simulation by using a maximum delaying time calculated by the calculation part 16.

Method and system of checking for open circuit connections within an integrated-circuit design represented by a hierarchical data structure

Abstract: An integrated-circuit design is provided which is represented by a hierarchial data structure. In accordance with the method and system of the present invention, an integrated-circuit design which includes at least one parent circuit represented by a set of parent circuit level data and at least one child circuit represented by a set of child circuit level data. For an open circuit connection within the child circuit, a determination is made as to whether or not the open circuit connection is permissible. In response to a determination that the open circuit connection is permissible, another determination is made as to whether or not the number of I/O pins within the child circuit is greater than the number of open circuit connections within the child circuit. In response to a determination that the number of I/O pins within the child circuit is greater than the number of open circuit connections within the child circuit, the set of child circuit level data is integrated into the set of parent circuit level data. Finally, a determination is made as to whether or not the open circuit connection is closed within the integrated set of parent circuit level data. An error message will be displayed if the open circuit connection is not closed within the integrated set of parent circuit level data.

Universal electronic building blocks

Abstract: The utility model relates to a universal electronic building block which is composed of an insulating installed bottom board, various element blocks, a conducting wire block and a shim. When a circuit is assembled, a stereo multilayered structure is adopted to carry out assembly without using a flexible conducting wire at all, and the utility model can be rapidly assembled into various circuits directly according to a schematic circuit diagram, such as electric lights, electric fans, music doorbells, alarms, oscillators, sound controllers, light controllers, radios, etc. Assembled objective circuits are completely same as the schematic circuit diagram, and the utility model has the advantage of specially good direct viewing performance and is suitable for electronic intelligence toys and teaching aids.

Difference display device

Abstract: PROBLEM TO BE SOLVED: To shorten the time for design by processing difference between graphic information and logic information before and after editing, changing display attribute of the difference and displaying the graphic information. SOLUTION: Based on logic information and graphic information, a 1st graphics display device 18 displays a circuit diagram and based on logic information and graphic information, a 2nd graphics display device 20 displays a printed board layout drawing. By referring to a difference information list prepared from a net list and an attribute value list, a CPU 10 displays the difference of logical connection information on the printed board layout drawing displayed on a 2nd graphic editor window for board layout according to the previously set display method of differential information. Further, when changed component are proper, an operation for instructing for reflecting the change is performed and processing is performed to fixedly reflect the change in a prescribed data base.

Method, apparatus and system for analyzing failure of measured device

Abstract: A method for analyzing failures and an apparatus for analyzing failures are provided in which failed portions can easily be specified with high precision in a short time by using an emission analyzing apparatus without analyzers depending on designers. The coordinates of an emitting portion on an emission image which is detected by an emission analyzing apparatus are automatically recognized (Step S5). The same coordinates are automatically converted into the coordinates on a layout pattern (data) (Step S7). An emitting portion on a layout pattern is automatically displayed (Step S11). The name of a node on a net list (data) of the emitting portion is automatically recognized according to the coordinates on the layout pattern (Step S12). The name of an emitting node is automatically displayed on a net list (Step S13). Furthermore, an emitting node on a circuit diagram (data) is automatically displayed as an emitting portion on a circuit diagram based on the emitting node name (Step S15).

Optical recognition of electrical circuit drawings

Abstract: This paper presents an optical recognition system for electrical circuits drawing. The system uses computer vision techniques to analyze the circuit's drawing and produces a circuit description program suitable for analysis by circuit analysis programs such as SPICE. The algorithm proposed uses a variety of machine vision techniques to locate the circuit nodes and isolate the circuit components. Moments' invariant descriptors are then used to for the recognition of both elements and values.

Fault analytic method for electrical circuit

Abstract: PROBLEM TO BE SOLVED: To provide a fault analysis method for an electrical circuit for improving the safety designing of the electrical circuit by simulating on an information arithmetic processor. SOLUTION: When an inspecting person inputs circuit information showing the constitution of a previously set electrical circuit to the editor picture of a circuit diagram editor 1, the editor 1 automatically generates a net list being its circuit information and the net list is outputted to a net list preparing part for simulation 2. The preparing part 2 automatically prepares plural kinds of net list groups for verification in which connection nets being the constituting element of the net list are in a short-circuited state or an open state. The prepared net list groups are given to a simulator 3. A result comparing part 4 compares the analytic result of the simulator 3 and the net list to automatically analyze whether or not abnormality is generated at the constitution element of the electrical circuit with respect to the short-circuited state of the opened state of the connecting net.

Line system analyzer

Abstract: PROBLEM TO BE SOLVED: To easily generate the model drawing of a line system as an analytic object while effectively utilizing a circuit diagram and further to let a user easily grasp the conditions of arrangement, wiring and performance distribution of the line system. SOLUTION: When the board circuit diagram of an analytic object net prepared by CAD exists at the generating of transmission line model, for example, an automatic transmission line model converting part 112 extracts the board circuit diagram information of the analytic object net from a board circuit diagram storage part 204, automatically converts the board circuit diagram information to the transmission line model while using an input/output library stored in a library storage part 204, stores the information of the provided transmission line model into a transmission line model storage part 207, and displays it on a graphic display 201.

Circuit design supporting method and device therefor

Abstract: PROBLEM TO BE SOLVED: To make the connection state of an element extending over a page visually observable and to the efficiency of the preparation/edition/confirmation work of a circuit diagram by displaying a merge processing circuit diagram on the same screen as the circuit of an edition object page. SOLUTION: The input circuit diagram 1 corresponding to a page, which is an edition object, is displayed on a display part 6. On the displayed circuit diagram, an interpage terminal, in which connection information is to be known, is selected by an input device 2. Next, the reading of the connection data of a desired page is performed by a memory part 4, and the extraction of the inter-page terminal of an opposite party which is to be connected with an inter- retrieval object page terminal and an element to be connectedwhich is connected with the terminal is performed. The page number of a page, in which the extracted element to be connected exists, is stored in the memory part 4. When the extraction of all the elements is finished, the extracted element to be connected is arranged on the of the side inter-retrieval object page selected at first, a merge processing of drawing net is performed and the merged circuit diagram is displayed on the same screen.

System for generating analog part deleted hardware description

Abstract: PROBLEM TO BE SOLVED: To automatically generate hardware description for logic verification from a circuit diagram of an electronic circuit without changing circuit diagram information by adding deletion information effective for the automatic generation of hardware description to analog parts such as resistance parts unnecessary for the logic verification of the circuit diagram of the electronic circuit. SOLUTION: A delition information adding means 15 adds deletion information to resistance parts unnecessary for the logic verification of circuit diagram data A and adds deletion information also to resistance parts for circuit diagram data B. Then a logical connection extracting means 17 extracts the connection information of the circuit diagram data. A deletion information discriminating means 18 discriminates the deletion information of each part from the extracted connection information. As to a part to which deletion information is added, an analog parts deleting means 19 deletes the information of the part from the connection information and changes the connection information of a network connected to the part to be deleted. Then a hardware description generating means 20 generates hardware description from the connection information of the changed circuit diagram data.

Method for calculating degree of freedom of logic function mapped to lut type fpga and method for optimizing circuit while using degree of freedom

Abstract: PROBLEM TO BE SOLVED: To express much higher degree of freedom of a logic function by calculating the degree of freedom of the logic function while expressing it as the cluster of paired logic functions. SOLUTION: A device reads circuit diagram data mapped from another function block to a look-up table(LUT) type field programmable gate array(FPGA) stored in a storage device 11, calculates the degree of freedom of the logic function in that circuit through a calculation part 13 and stores the result in a storage device 15, and this result is to be used by another function block 17. Then, on the condition that an external logic is not to be changed, while considering that the internal logic of an LUT can be freely changed, the degree of freedom of the logic function expressed by the LUT in the circuit or the connection between the LUT is calculated, by expressing it as the cluster of paired logic functions to be distinguished at least when this logic function becomes '1' or '0'.

Layout verification method and circuit simulation method

Abstract: PROBLEM TO BE SOLVED: To automatically verify an LVS on condition that a SPICE net list is extracted from a layout pattern. SOLUTION: An external SPICE net list extraction tool 1 extracts the SPICE net list 4 from the layout pattern 3 and a net lister 5 which is internally provided extracts a circuit diagram net list 6 from circuit diagram data 2; and then a net comparator 7 which is internally provided compares the circuit diagram net list 6 and SPICE net list 4 with each other to verify the layout pattern 3.

Method and apparatus for determining locations of circuit elements including sequential circuit elements

Abstract: A circuit element placement method and apparatus in which circuit elements can surely be placed in a short time even if a circuit scale is increased. For this purpose, there is sequentially executed a first step of determining placement coordinates of sequential logic circuit elements among many circuit elements to be placed and a second step of determining placement coordinates of circuit elements other than the sequential logic circuit elements with consideration given to the placement coordinates of the sequential logic circuit elements, determined in the first step. The method and apparatus are applicable at a time of design of an integrated circuit such as LSI, or a circuit on a printed wiring board.

Automatic layout method for semiconductor integrated circuit

Abstract: PROBLEM TO BE SOLVED: To shorten a layout period and prevent misdesigning by laying out a division-specified part wholly using an automatic wiring function SOLUTION: An automatic layout tool converts data on a circuit diagram which are inputted in a step S1 into data on a net list in a step S2 The automatic layout tool arranges general elements in a step S3 and arranges macros for wiring division in a step S4 The automatic layout tool wires the general elements and macros for wiring division in a step S5 directly by the automatic wiring function without performing manual wiring operation

Method and system for performing quantitative sneak circuit analysis

Abstract: A method and system for determining bi-directional sneak current paths of an electrical/electronic circuit. The electrical/electronic circuit is converted into a corresponding schematic having a plurality of components and a plurality of line segments. A segment identifier is then inserted into each of the plurality of line segments. Next, a DC analysis is performed on the electrical/electronic schematic for each possible switch position combination to obtain a current value for each of the plurality of components. Bi-directional sneak current paths are then determined based on the plurality of segment identifiers and the current value for each of the plurality of components.

Layout pattern testing method

Abstract: PROBLEM TO BE SOLVED: To rigorously test a power source and ground by tracking a pattern connected between one and other hierarchical layers, giving information of the other layers to the pattern, and collating layout information with circuit diagram information to test a layout pattern. SOLUTION: An intra-cell connection information extracting means 101 executes for cells the equipotential tracking and element informing of layout data of an electronic circuit under test, having a hierarchical structure, to obtained connection information per cell. In an inter-hierarchy connection informing step 102, the overlap of the cells is investigated by the top down to track the connection between the hierarchical layers, and the obtained information is given to cells to be connected and common upper level cells. A net name recognition information automatically giving means 103 gives net name information to all the patterns concerning the power and ground interconnections. A detecting means 104 collates the connection information obtained by the means 101 with cell connection information of logic circuit diagrams in the electronic circuit.

Logic design support device

Abstract: PROBLEM TO BE SOLVED: To easily set and change a supply voltage without error and to simulate a logic without duplication of logical operation information with respect to the logic design of a circuit where plural supply voltages exist together SOLUTION: The constitution of a design circuit shown by circuit diagram data 14 generated based on design information inputted by a user is displayed by a hierarchical tree display part 16, and a supply voltage setting part 18 generates supply voltage data 20 of each block of the design circuit based on the operation of the user who saw this constitution Meanwhile, a delay extraction part 30 uses hierarchical expansion data 24 of the design circuit generated by a hierarchical expansion part 22, supply voltage data 20, and delay information libraries 26 and 28 prepared for respective supply voltages to generate delay data 32 after hierarchical expansion A logic simulation part 36 uses this delay data 32, hierarchical expansion data 24, and a logical operation library 34 common to respective supply voltages to perform the logic simulation

Method for improving delay of integrted circuit

Abstract: PROBLEM TO BE SOLVED: To reduce the manhour and shorten the period for the correction of circuit diagram data which are required for the improvement of delay. SOLUTION: A step S1 executes delay analysis processing based upon circuit diagram data A by a delay analysis tool. At the time of detecting that the delay of path does not satisfy an object delay in a step S2, a flip flop circuit and an output terminal to be the start points of paths not reaching the object delay are retrieved based upon the data A and result data B by usteps S3, S4. If it is judged that the unsatisfication of the object delay is a delay caused by a scanning path in a step S5, a step 7 reconnects the scanning path to an inverted output terminal of which polarity is inverted from that of the output terminal retrieved by a step 6 and inserts an inverter circuit to the scanning path to hold the equivalency of the polarity.

Preparing device and translating device for circuit diagram

Abstract: PURPOSE: To give a circuit description of high readability for gathering information for monitoring start conditions, operation conditions, etc, into a memory of one word with a small-scale circuit diagram for a programmable controller use circuit diagram CONSTITUTION: It is made possible to describe a word memory allocation symbol A in a specific column in the output condition part (e) of an output description line 100 The symbol 'A' is a symbol indicating that a signal of an input description line or an arithmetic result is written at the bit position specified with the word memory bit position symbol (hexadecimal value) described in the same column with the symbol 'A' Further, it is made possible to describe an emphasized display symbol 'F' in a specific column in the output condition part (e) of the output description line 100 This symbol 'F' is a symbol indicating that the word memory bit symbol (hexadecimal value) described in the same column with the symbol 'F' is emphasized and displayed according to the contents of a memory corresponding to the output description line where the symbol 'F' is described

Circuit diagram design supporting device

Abstract: PROBLEM TO BE SOLVED: To prepare a circuit diagram to be easily viewed and read by executing processing allocated to a command button at the time of detecting a click event corresponding to the command button and changing the property of element information so as to edit a symbol graphic during the preparation of the circuit diagram. SOLUTION: A symbol graphic is specified and element information in the graphic is extracted. Whether the element information exists or not is checked, and when the element information exists, whether the change of its property is permitted or not is checked. When the checked result is true, whether the element information is grouped with other element information or not is checked, and when the information is grouped and the element information has a common changeable property in the group, the group is defined, the objective property of single element information or grouped element information is changed and a user 15 urged to select the rewriting of the changed symbol graphic in a library or the addition of the changed symbol graphic to the library as a new graphic.

Method and apparatus for verifying and electrical configuaration using a psuedo-element pattern

Abstract: To prevent a false error from occurring in the comparison and collation between circuit connection information and a mask pattern, a method and apparatus for verifying an electrical configuration include designing a mask pattern from a circuit diagram, extracting output terminals having equal potential from the mask pattern, and inserting at least one first pseudo-element pattern between the output terminals.

Error portion displaying method and layout verification display device

Abstract: PROBLEM TO BE SOLVED: To provide an error portion display technique by which a work specifying what drawing of which hierarchy an error exists in, can be easily performed even if the hierarchy exists in a circuit diagram, in the layout verification of a semiconductor integrated circuit. SOLUTION: This device is a display device for layout verification by the hierarchical structures of semiconductor integrated circuits such as a large-scale DRAM and a high speed microcomputer, etc. The device is composed of an error result data file 1 after layout verification, an error portion display control part 2, an emphasis display part 3 on hierarchical browser, an emphasis display part 4 on layout pattern, an emphasis display part 5 on circuit diagram, a hierarchical browser device 6, a layout pattern editing device 7 and a circuit diagram editing device 8, etc. As a result of the verification by a layout verification device 11 based on the data of a layout pattern data file 9 and a circuit diagram data file 10, an emphasis display is performed for the hierarchies from a high order circuit diagram to a lower order circuit diagram which include an error portion, in particular.