Showing papers on "Circuit diagram published in 2001"

Microfluidic design automation method and system

Abstract: The present invention generally relates to microfluidics and more particularly to the design of customized microfluidic systems using a microfluidic computer aided design system. In one embodiment of the present invention a microfluidic circuit design method is provided. The method includes developing synthesizable computer code for a design. Next, a microfluidic circuit schematic, including a plurality of symbols for microfluidic components, is generated either interactively or using the synthesizable computer code. The microfluidic circuit schematic is then functionally simulated. The microfluidic components are placed and routed on a template to form a physical layout. Then the physical layout is physically simulated using dynamic simulation models of the microfluidic components; and the physical layout is written to a layout file.

The sizing rules method for analog integrated circuit design

Abstract: This paper presents the sizing rules method for analog CMOS circuit design that consists of: first, the development of a hierarchical library of transistor pair groups as basic building blocks for analog CMOS circuits; second, the derivation of a hierarchical generic list of constraints that must be satisfied to guarantee the function of each block and its reliability with respect to physical effects; and third, the development of an automatic recognition of building blocks in a circuit schematic. The sizing rules method efficiently captures design knowledge on the technology-specific level of transistor pair groups. This reduces the preparatory modeling effort for analog circuit synthesis. Results of industrial applications to circuit sizing, design centering, response surface modeling and analog placement show the significance of the sizing rules method. Sizing rules especially make sure that automatic circuit sizing and design centering lead to technically meaningful and robust results.

Creating a PC board (PCB) layout for a circuit in which the components of the circuit are placed in the determined PCB landing areas

Abstract: A method and apparatus for PCB layout of a circuit simulated over a network is provided. Techniques are provided for designing a circuit that satisfies user-specified functional requirements received over a network. Based on the specified requirements, components and a topology for constructing the circuit are automatically determined. The components determined during this operation have operational values such that, when the components are arranged according to the topology to form the circuit, the circuit satisfies the user-specified functional requirements. The components are placed on a PC board having landing areas designed to accommodate all of the anticipated component sizes for the type of circuit being designed. The PC board may be cropped to the desired size. The PCB may be cropped automatically or manually by the user. The component and topology information may be used to generate a schematic diagram that is delivered in a web page to the user over the network. The user may thermally and electrically simulate the designed circuit. Many characteristics of the PC board may be adjusted to produce an accurate circuit.

A 1.57 GHz fully integrated very low phase noise quadrature VCO

Abstract: A very low phase noise quadrature VCO is presented, featuring an inherently better figure of merit than the existing architectures. Through an improved circuit schematic and a special layout technique, the phase noise of the circuit could be lowered to stand amongst the lowest published. The circuit draws 15 mA from a 2 V supply. The phase noise is -136.5 dBc/Hz@600 kHz and the tuning range is 24% wide at a center frequency of 1.57 GHz. The figure of merit outperforms other published QVCOs.

Method to perform thermal simulation of an electronic circuit on a network

Abstract: A method and apparatus for thermally simulating a circuit over a network is provided. Techniques are provided for designing a circuit that satisfies user-specified functional requirements received over a network. Based on the specified requirements, components and a topology for constructing the circuit are automatically determined. The components determined during this operation have operational values such that, when the components are arranged according to the topology to form the circuit, the circuit satisfies the user-specified functional requirements. One or more web pages that identify the components are then delivered to the browser over the network. The component and topology information may be used to generate a schematic diagram that is delivered in a web page to the user over the network. The user may thermally simulate the designed circuit. Many characteristics of the board may be adjusted to provide an accurate thermal simulation. The user may place an order over the network for one of the components, a kit of all of the components, a custom made circuit made from the components, and/or a prefabricated circuit that is functionally similar to the one that was designed.

Method for configuring an electrical installation and corresponding configuration device

Abstract: A network map is determined, either in the operating direction from the feed circuit to the load in the load circuit, or backward on the basis of the loads in the load circuit to the data for the feed circuit. The feed circuit and the load circuit are coupled to a virtual interface, at which secondary distribution panels can be interconnected. The schematic procedure, in conjunction with appropriate computation rules and visualization in a network map that is obtained, allows the configuration process to be carried out even by those who are unskilled.

Computer aided method of circuit extraction

Abstract: A method and apparatus for extracting circuit design information from a pre-- existing semiconductor integrated circuit (IC) or at least a portion thereof is described. It includes imaging at least a portion of two or more physical layers of the pre--existing IC to obtain stored electronic images of the physical IC layers, converting the stored electronic images of the physical IC layers to a vector format, horizontally and vertically aligning the vector format data of the electronic images of the physical IC layers, and providing a multi-layer display of the aligned vector data. A net- list or schematic is generated from the multi-layer display of the vector data. The netlist and/or schematic may be generated as a number of individual pages by providing a template of circuit elements and placing a circuit element over a portion of the display corresponding to the circuit element. The template of circuit elements may include transistors, logic gates or complex circuit blocks. The vector data may be altered to correct errors in the images or manipulated to correct the alignment of the images. In addition, the schematic may be traced to the image of the physical IC layer.

Methods, systems, and computer program products for designing an integrated circuit that use an information repository having circuit block layout information

Abstract: An integrated circuit (IC) is designed by generating a circuit diagram of the IC using one or more blocks. An information repository is provided that contains layout information that is associated with one or more template blocks. A symbol layout abstraction model is then generated by associating the layout information that is associated with one or more of the template blocks with at least one of the circuit diagram blocks of the IC.

Circuit design method and circuit design apparatus

Abstract: Route nets having at least one current path through which a current flows are extracted from among a plurality of route nets each representing a line that interconnects elements of an electronic circuit in electrical connecting relationship from information on an electronic schematic. The extracted route nets is separated into a first subnet of lines where currents flow and a second subnet of lines where no currents flow. A route is determined for each of the first and second subnets. Points on the routes for the first and second subnets are interconnected by another route.

System and method for disabling schematics

Abstract: A system and method for designing schematic diagrams of electronic circuits is provided. A library of electronic components represented in graphical form are selectable by a user for inclusion into a schematic diagram. The components are connected together to define a circuit that performs a function. In order to simulate and test a particular portion of the circuit rather than the entire circuit, the present invention provides a disabling routine that disables portions of the circuit not to be included in the simulation. The present invention allows a circuit designer/tester to focus on desired areas of a circuit while ignoring others.

Integrated circuit and method of designing integrated circuit

Abstract: An integrated circuit has a functional circuit for achieving an actual operation function of the integrated circuit, and a redundant circuit that is used based on a changeover from a defective circuit within the functional circuit. This integrated circuit has I/O regions to carry out a signal transmission between the functional circuit and the outside. Each I/O region incorporates fuse boxes for changing over from a defective circuit to the redundant circuit.

Circuit including a built-in self-test

Abstract: A circuit includes a built-in self-test, wherein the test coverage of a tested logic circuit is improved given the utilization of a fixed standard interface. Besides a direct interface, the complex circuit has an additional indirect interface, which connects a structural test device to a functional circuit.

Circuit operation verifying method and apparatus

Abstract: In the circuit operation verifying method, initialization includes inputting circuit diagram data (a net list), specification information on respective circuit elements, and input data representing waveforms with time of voltages or currents used for operation simulation, and storing the circuit diagram data to memory. Operation of a semiconductor circuit to be verified is simulated using the circuit diagram data and the input data, and momentary voltage/current values at input terminals and the like of the circuit elements are stored in the memory. During the operation simulation, whether or not the circuit elements satisfy their voltage/current specifications and time specifications are concurrently verified based on the voltage/current values stored in the memory.

Circuit modeling and feedback controller development of the 8.4MW modulator/regulator power system for the electron cyclotron heating facility upgrade at DIII-D

Abstract: As part of the Electron Cyclotron Heating (ECH) Facility upgrade at DIII-D an 8.4 MW Modulator/Regulator Power System was designed and constructed using acquired hardware from the Mirror Fusion Test Facility (MFTF) at Lawrence Livermore National Laboratory (LLNL) program as a foundation. 1 Design changes in the feedback control of the modulator/regulator (M/R) was motivated by the need for improved output voltage regulation and improved capability to modulate the output voltage consistent with reference command signals containing modulation patterns (typically square wave). The regulation characteristics of the old ECH M/R power system had previously constrained gyrotron operation due to marginal voltage control loop stability and slow response to voltage step changes. The technical approach was to develop models of the circuit functions of the M/R controller from the circuit diagrams, and then examine the control characteristics using circuit analysis software. MATLAB® Simulink® and Intusoft IsSPICE4® (SPICE) codes were used to examine the control issues. These analysis software tools were used to simulate the controller functions and yielded identical results. The SPICE circuit model was selected as a baseline for future maintenance by the engineering staff. The analysis of the controller model blocks provided the needed information to modify the controller circuits. Changes made to the controller included addition of a voltage feedback loop around the grid driver amplifier for the power tetrode control grid in the M/R, and changes to the feedback loop compensation of the main error amplifier. The implemented revised controller performance matches the model performance predictions remarkably well. This paper describes the circuit models, implementation of the revisions to the controller, and recent operational results.

Electronic teaching materials

Abstract: PROBLEM TO BE SOLVED: To provide electronic parts needed for electronic experimetation inexpesively and in an easy-to-handle form. SOLUTION: In this electronic teaching materials, leads 14 of electronic parts such as diode 10a, resistor 10b, light emitting diode 10c, transistor 10d, capacitor 10e and IC 10f are inserted into holes 12 of a universal board 10 and the parts are held on the board without being soldered, Numerals and letters of the alphabet are printed on the surface of the universal board 10 to show positions of these electronic parts. When a user picks up electronic parts for realizing a functional circuit from the board 10 while seeing a circuit diagram and mounts the picked up parts on the board 10 from which parts are removed and which becomes vacant or on another wiring board and the user solders them to wirings, the user can produce a desired functional circuit to perform experimentation on the circuit.

Circuit simulating apparatus performing simulation with unnecessary ciruit disconnected

Abstract: A circuit simulating apparatus includes a netlist extracting unit extracting a netlist from circuit diagram data, an unnecessary circuit disconnecting unit forming a netlist with an unnecessary circuit disconnected, from the netlist extracted by the netlist extracting unit, based on an unnecessary circuit disconnecting terminal designated by an unnecessary circuit disconnecting terminal designating unit, and a circuit simulation unit performing a circuit simulation using a simulation input file formed by using the netlist with the unnecessary circuit disconnected. As the circuit simulation is performed using the simulation input file formed from the netlist with the unnecessary circuit disconnected, the time necessary for the circuit simulation can be reduced.

Method and device for automatic optimal location of an operation on an integrated circuit

Abstract: The invention concerns a method and an installation for automatic optimal location of an intervention procedure on a printed circuit which consists in retrieving polygons accessible from topographical description data and data representing a circuit diagram The method consists in: determining, for each step, different execution options corresponding respectively to each of the different accessible polygons, and calculating and assigning a rating to each execution option on the basis of the depth of each possible initial polygon relative to the surface of intervention, and accessibility parameters of each possible initial polygon, and in automatically determining the execution option to be used to execute each step of the intervention procedure, by digital optimisation calculation using the ratings assigned to the different execution options of each step of the intervention procedure

Device, method and program for generating logic circuit diagram

Abstract: PROBLEM TO BE SOLVED: To easily prepare and change a logic circuit diagram on which an FPGA(field programmable gate array)/PLD(programmable logic device) is mounted without accompanying an increase in man-hour or quality degradation of the circuit diagram. SOLUTION: In logic circuit diagram preparation for a printed circuit board on which the FPGA/PLD is mounted, a pin correspondence table reading processing part for reading a pin correspondence table on which pin numbers for the FPGA/PLD, netnames on a circuit for signals connected to pins of the FPGA/PLD and information of input and output directions of connections between pages of a net on the circuit are described, a symbol arrangement processing part for arranging a circuit symbol of the FPGA/PLD to an optional page on the circuit diagram, and a net connection processing part for connecting a net to a pin of the circuit symbol of the FPGA/PLD arranged on the circuit diagram are provided, and a logic circuit diagram for a page on which the connection of the FPGA/PLD is described is automatically prepared by inputting the pin correspondence table.

Method for outputting circuit diagram connection information

Abstract: PROBLEM TO BE SOLVED: To prevent correction omission of a symbol library in updating symbol library information on circuit diagram data. SOLUTION: A library preparing means 1 prepares a symbol library of a logical circuit. The symbol library 2 stores the latest symbol library information 32. A circuit diagram inputting means 3 outputs circuit diagram data 43. A circuit diagram data storing means 4 stores the circuit diagram data 43 and outputs circuit diagram data 39, symbol terminal information 19, and symbol ID 20. A symbol acquiring means 8 sequentially acquire the symbol IDs 20 and outputs a symbol ID 21, a symbol ID 30 and an update control signal 41. A symbol terminal information A acquiring means 5 inputs the symbol terminal information 19 and the symbol ID 21 and outputs terminal information 22. A terminal information A storing means 6 inputs the terminal information 22 and outputs terminal information 26.

Apparatus and method for automatically verifying a designed circuit

Abstract: This invention provides an apparatus and a method for automatically verifying a designed semiconductor integrated circuit (LSI). The apparatus verifies a circuit generated by a generator for generating a circuit diagram of the whole LSI in accordance with the arrangement of basic cells which define a predetermined circuit unit. At least one of basic cells includes a verification symbol specifying a name and verification contents of a node to be verified. The apparatus analyzes a circuit diagram of the whole LSI generated in accordance with the arrangement having a cell including verification symbols to extract names and verification contents of the nodes to be verified, generates a verification pattern in accordance with the extracted node name and verification contents, executes a circuit simulation by using the verification pattern, analyzes the simulation result, and determines whether a the verified node is accepted or rejected.

System for and method of designing and manufacturing a semiconductor device

Abstract: A system and method are provided for designing and manufacturing a semiconductor device, such as part of an integrated circuit. A template comprising a basic circuit diagram of a discrete circuit block and corresponding design equations are selected from a library. Desired performance parameters are selected and the value of one or more components of the circuit block are determined to allow the block to achieve the desired performance parameters.

Design device for printed circuit board

Abstract: PROBLEM TO BE SOLVED: To evade a trouble in a designing step of a printed circuit board without relying on the experiences and perception of an expert. SOLUTION: This device includes a circuit diagram input tool 302 which produces a circuit according to the part information showing the parts to be mounted on a printed circuit board and the connection information on the interconnection of the parts, a layout input tool 303 which performs a layout about the arrangement of component parts of the circuit board and the circuit on the basis of the circuit diagram produced by the tool 302, an input part 304 which inputs the information to be given to both tools 302 and 303, a display part 305 which shows the circuit diagram information produced by the tool 302 and the layout information obtained by the tool 303 and an estimation means 307 which estimates an impedance discontinuous part on the basis of the layout information.

Diagnostic circuit box for 12-volt automotive applications for detection of circuit faults especially in relay circuits using an internal free-wheel diode, so that a diagnosis can be made without requiring a full circuit diagram

Abstract: Device for connection between two relays, such as a free-wheel relay with an internal diode as used in a motor vehicle Device comprises a box (10), two two-color diodes (6, 7) and two 5-wire or more connection cables (16, 17) having male (12) and female (11) connections The device includes diagnostic circuits for indicating the relay condition, such as its polarity, circuit continuity and the efficiency of the internal free wheel relay diode

Electronic circuit analyzer

Abstract: PROBLEM TO BE SOLVED: To provide an electronic circuit analyzer capable of transmitting items required for mask pattern generation written in a conventional 'mask pattern instruction book' just by delivering an electronic circuit to a mask pattern generator SOLUTION: The size of a circuit symbol is reflected in a circuit diagram so as to correspond to the size at the time of an actual layout Since the circuit diagram is utilized as a detailed instruction book regarding a mask pattern as it is, just by delivering an electronic circuit diagram to the mask pattern generator, a mask layout satisfactory to an analog circuit design engineer is obtained

Order determination for frequency compensation of negative-feedback systems

Abstract: To maximize the bandwidth of dedicated negative feedback amplifiers by passive frequency compensation, the order of the amplifier needs to be known. Here a method is introduced to determine the order of a circuit with negative feedback. It is shown that the slim of poles in the negative feedback loop, i.e. the loop poles, can be used to determine the order of the amplifier. These loop poles, can be found relatively easily from the circuit diagram and thus the order of the circuit is also relatively easily found.

Device and method for supporting substrate design

Abstract: PROBLEM TO BE SOLVED: To effectively utilize information on a registered block when a substrate specification or the like used for designing the registered block is different from the specification of a design object substrate in utilizing that information concerning a substrate design supporting device suitable for supporting printed circuit board design SOLUTION: A circuit block library is provided for storing information on the registered block of an existent circuit block and information on the substrate specification used for designing the registered block The registered block having the same configuration as a circuit block included in a circuit diagram data as the design object is retrieved from the circuit block library The difference between the substrate specification corresponding to the retrieved registered block and a request substrate specification requested to the design object substrate is grasped A circuit block deforming part 2 is provided for converting the information on the retrieved registered block on the basis of the difference between both the substrate specifications

Cross-talk verifying device and method

Abstract: PROBLEM TO BE SOLVED: To provide a device capable of efficiently and highly precisely realizing cross-talk verification by automatically selecting a coupling capacitance whose influence on a circuit operation should be considered from a circuit operation pattern and layout data. SOLUTION: In a node/coupling capacitance selecting part 4, simultaneously changing nodes (NDI) are extracted from an input pattern (IP) and a net list (NTL) from a circuit diagram, and a coupling capacitance (CCI) which is not less than a designated value is extracted, and the node whose coupling capacitance should be considered is judged from the extraction result, and the information (ND/CC) of the judged node and the coupling capacitance is generated/held by a means 43. Then, simulation is executed including the coupling capacitance of the selected node, and the simulation result is waveform-displayed. COPYRIGHT: (C)2003,JPO

Semiconductor circuit designing apparatus and a semiconductor circuit designing method in which the number of steps in a circuit design and a layout design is reduced

Abstract: A semiconductor circuit designing apparatus includes a circuit design unit executing and an inspection item database section. The circuit design unit executes a logical design of a semiconductor integrated circuit. In the inspection item database section a circuit feature of the semiconductor integrated circuit corresponds to an inspection item of a inspection to be executed before a layout design of the semiconductor integrated circuit is executed. The circuit design unit generates a target circuit feature information indicating the circuit feature of a target semiconductor integrated circuit of the semiconductor integrated circuit of which the logical design should be executed. The circuit design unit obtains a target inspection item of the inspection item corresponding to the target circuit feature information from the inspection item database section. The circuit design unit executes the logical design of the target semiconductor integrated circuit in reference to the target inspection item.

Module recognition and its application to LVS of ASIC

Abstract: LVS (Layout Versus Schematic) is an important procedure in ASIC design. LVS includes 2 steps: extraction of devices and net-lists from layout with an EDA system to form the schematic, the so-called "extracted schematic", and identification and verification of the extracted schematic with another schematic designed independently upon layout. The former is more important than the latter. Module recognition plays a very effective role during extraction of schematic from layout. The theoretical principle is described in the paper, followed by a detailed description of an actual method, with some examples of bipolar analog ASIC design.

Method for verifying layout data

Abstract: PROBLEM TO BE SOLVED: To provide a method for verifying layout data, by which a mask layout pattern and a circuit diagram can be compared and collated in a short time without preparing a circuit diagram for verification irrespective of the number of emitter holes in a lateral PNP transistor. SOLUTION: This layout data verifying method uses a computer to verify whether an integrated circuit mask layout pattern prepared based on a circuit diagram is equivalent to the circuit diagram. Element connection information is extracted based on a base layer in the integrated circuit mask layout pattern.