Showing papers on "Clock domain crossing published in 2019"

A Systematic Approach to Clock Failure Detection

Abstract: Many of today's chips comprise multiple clock domains and some even have multiple clock sources. This makes supervision of the correct operation of a clock increasingly important. Rather than promoting a specific approach for clock failure detection, this paper tries to provide a systematic overview of the available options. To this end, requirements and principles are identified and discussed first, and then related implementations are shown. These are partly revisiting existing solutions from the literature that are put into the context, and partly constituting novel solutions. The implementations are evaluated according to several criteria, like detection latency, implementation efforts, and, most notably, potential for metastability issues. The purpose of the paper is to give the designer a guideline, showing which techniques are available, along with a critical assessment that shall help in making the appropriate choice for a given application.

Metastability-Resilient Synchronization FIFO for SFQ Logic

Abstract: Digital single-flux quantum (SFQ) technology promises to meet the demands of ultra low power and high speed computing needed for future exascale supercomputing systems. The combination of ultra high clock frequencies, gate-level pipelines, and numerous sources of variability in SFQ circuits, however, make low-skew global clock distribution a challenge. This motivates the support of multiple independent clock domains and related clock domain crossing circuits that enable reliable communication across domains. Existing J-SIM simulation models indicate that setup violations can cause clock-to-Q increases of up to 100%. This paper first shows that naive SFQ clock domain crossing (CDC) first-in-first-out buffers (FIFOs) are vulnerable to these delay increases, motivating the need for more robust CDC FIFOs. Inspired by CMOS multi-flip-flop asynchronous FIFO synchronizers, we then propose a novel 1-bit metastability-resilient SFQ CDC FIFO that simulations show delivers over a 1000 reduction in logical error rate at 30 GHz. Moreover, for a 10-stage FIFO, the Josephson junction (JJ) area of our proposed design is only 7.5% larger than the non-resilient counterpart. Finally, we propose design guidelines that define the minimal FIFO depth subject to both throughput and burstiness constraints.

qCDC: Metastability-Resilient Synchronization FIFO for SFQ Logic

Abstract: Digital single-flux quantum (SFQ) technology promises to meet the demands of ultra low power and high speed computing needed for future exascale supercomputing systems. The combination of ultra high clock frequencies, gate-level pipelines, and numerous sources of variability in SFQ circuits, however, make low-skew global clock distribution a challenge. This motivates the support of multiple independent clock domains and related clock domain crossing circuits that enable reliable communication across domains. Existing J-SIM simulation models indicate that setup violations can cause clock-to-Q increases of up to 100%. This paper first shows that naive SFQ clock domain crossing (CDC) first-in-first-out buffers (FIFOs) are vulnerable to these delay increases, motivating the need for more robust CDC FIFOs. Inspired by CMOS multi-flip-flop asynchronous FIFO synchronizers, we then propose a novel 1-bit metastability-resilient SFQ CDC FIFO that simulations show delivers over a 1000 reduction in logical error rate at 30 GHz. Moreover, for a 10-stage FIFO, the Josephson junction (JJ) area of our proposed design is only 7.5% larger than the non-resilient counterpart. Finally, we propose design guidelines that define the minimal FIFO depth subject to both throughput and burstiness constraints.

Method for synchronizing power charge-pump with system clock

Abstract: The proposed Power Management Integrated Circuit(PMIC) features the option to synchronize the charge-pump of a PMIC with the system clock, and then to swap and self-oscillate and skip pulses, when the digital controls of the PMIC send a first order to the charge-pump. The clock control circuitry of the PMIC also features the option for the charge-pump to then swap and use the system clock again, when the digital controls of the PMIC send a second order to the charge-pump. The designed transition of the clock from clock sync-mode to self-oscillate, and from self-oscillate back to clock sync-mode, does not present any phase discontinuity.

Methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniques

Abstract: Disclosed are techniques for verifying an electronic design using hierarchical clock domain crossing verification techniques These techniques identify an electronic design including a top hierarchy and one or more instances at a first child hierarchy below the top hierarchy The electronic design may be decomposed into a top hierarchy block for the top hierarchy and one or more child blocks for the one or more instances A plurality of data structures may be generated by separately processing the top hierarchy block and the one or more child blocks on one or more computing nodes One or more clock domain crossing structures may be identified in the electronic design at least by integrating the plurality of data structures

Asynchronous FIFO device

Abstract: The utility model provides an asynchronous FIFO (First In First Out) device with the depth of any even number, wherein a read (write) pointer adopts a special Gray code for coding. A read (write) pointer signal in the asynchronous FIFO is directly connected to the clock domain crossing synchronization module and is also directly connected to the RAM to serve as a read (write) address signal. The asynchronous FIFO does not need to additionally calculate or store the RAM address of the natural binary code.

Method and device for realizing asynchronous FIFO with low transmission delay at any depth

Abstract: The invention provides a method and a device for realizing asynchronous FIFO (First In First Out) with low transmission delay at any depth. By applying the method and the device, the increment of theread-write address in the clock domain is coded, the coded information has the characteristic of irrelevance between bits, and then the coded information is decoded in the clock domain of the oppositeside through clock domain crossing processing to obtain the address increment information. According to the invention, a read-write address cross-clock domain synchronization mode of asynchronous FIFO is designed as address increment transmission, and complete address information does not need to be transmitted any more; according to the method, an address increment encoding and decoding mode isdesigned, so that the problem of state instability occurring in a metastable state is harmless to system functions, the cross-clock processing logic complexity is simplified, and the asynchronous FIFOtransmission delay is reduced; according to the invention, the depth of the FIFO can be any value; the address cross-asynchronization can be completed within 2-3 beats, so that the transmission processing delay of the asynchronous FIFO can be shortened to 3-4 beats.

PANE: Pluggable Asynchronous Network-on-Chip Simulator

Abstract: Communication between different IP cores in MPSoCs and HMPs often results in clock domain crossing. Asynchronous network on chip (NoC) support communication in such heterogeneous set-ups. While there are a large number of tools to model NoCs for synchronous systems, there is very limited tool support to model communication for multi-clock domain NoCs and analyse them. In this article, we propose the Pluggable Asynchronous NEtwork on Chip (PANE) simulator, which allows system-level simulation of asynchronous network on chip (NoC). PANE allows design space exploration of synchronous, asynchronous, and mixed synchronous-asynchronous(heterogeneous) NoC for various system-level NoC parameters such as packet latencies, throughput, network saturation point and power analysis. PANE supports a large range of NoC configurations—routing algorithms, topologies, network sizes, and so on—for both synthetic and real traffic patterns. We demonstrate the application of PANE by using synchronous routers, asynchronous routers, and a mix of asynchronous and synchronous routers. One of the key advantages of PANE is that it allows a seamless transition from synchronous to asynchronous NoC simulators while keeping pace with the developments in synchronous NoC tools as they can be integrated with PANE.

Design of an Asynchronous Switch for Clock Domain Crossing Interfaces

Abstract: This paper proposes a design of an asynchronous switch interfacing circuit between any numbers of different local clock synchronous domains. The asynchronous switch will generate a slower clock frequency from different local clock modules and moderate the high rated clock domain to slow down its clock frequency without stopping or pausing any clock of them during the data communication phase. The proposed design is implemented using the CMOS 45nm technology of STMicroelectronics and simulated using timed VHDL model (Xilinx ISE Design Suite 12.1). The delay time is required to change the clock frequency is mathematically modeled. It is shown that the switching delay time depends on the number of multipoint communicating domains. The proposed system is designed to use a small number of circuit elements that results in conspicuous improvements in terms of power consumption, throughput, and circuit area. General Terms Clock FrequencySwitching Delay, Power Consumption, throughput

Clock circuit and method of operating the same

Abstract: A clock circuit includes a first latch circuit, second latch circuit, first trigger circuit and second trigger circuit. The first latch circuit is configured to generate a first latch output signal based on at least a trigger signal or an output clock signal. The second latch circuit is coupled to the first latch circuit, and configured to generate the output clock signal responsive to a control signal. The first trigger circuit is coupled to the second latch circuit, and configured to adjust the output clock signal responsive to at least the first latch output signal. The second trigger circuit is coupled to the first latch circuit and the first trigger circuit by a first node, configured to generate the trigger signal responsive to an input clock signal, and configured to control the first latch circuit and the first trigger circuit based on at least the trigger signal.

Clock domain crossing buffer

Abstract: Methods and systems for performing clock domain crossing The method may include receiving a start signal from an ingress domain delay device at a first egress domain delay device The start signal may be received at a first rising edge of an egress domain clock cycle The method may also include receiving, from the first egress domain delay device at a start receive device, the start signal at a second rising edge of the egress domain clock cycle The second rising edge may be N egress domain clock cycles after the first rising edge The method may also include incrementing, in response to receipt of the start signal by the start receive device, a buffer read pointer of the buffer by at least N buffer addresses, and reading, after incrementing the buffer read pointer, a second data unit from the buffer at a location indicated by the buffer read pointer