Showing papers on "Clock gating published in 1973"

Asynchronous clocking apparatus

Abstract: Clocking apparatus for complex and extensive data processing systems in which the functional logic circuit units are each provided with individual clocking circuits and the several clocking circuits are activated by a central control unit. Operation of the individual clock circuits is initiated by control unit signals and each clock circuit operates at an independent rate. The clocking system is readily adaptable to computer systems using large scale integration (LSI) since the clock circuits can be made a portion of each LSI chip and operated to control the functional logic circuits on that chip. At the conclusion of a functional cycle, a completion signal is transmitted to the central control unit which can then generate additional clock initiation signals as required. The clock circuits also include additional delay circuits which can be activated to add predetermined amounts of delay between selected clock output signals to permit remotely adapting the clock timing control to the requirements of a functional logic unit.

System clock for electronic communication systems

Abstract: The system clock of the present invention is designed in such a manner that it is ''''fail-safe,'''' and a single failure of any kind will not prevent generation of clock pulses. More particularly, the system clock consists of two identical clock cards wired for redundant operation. One clock card functions as the main system clock (MSC), and the other functions as the standby system clock (SSC). Clock pulses normally are provided by the MSC to the appropriate subsystem timing generators, however, if a fault develops in the MSC, the pulse output of the MSC is inhibited and the function of providing pulses is transferred to the SSC. The transfer feature always takes place when an ALARM lead on the MSC goes to a logic one.

Fault tolerant clock apparatus utilizing a controlled minority of clock elements

Abstract: A fault-tolerant clock apparatus, insensitive to occurrence of faults or failures in components thereof, providing an output clock pulse for use in fault-tolerant digital computers and the like.

Elimination of transient errors in a data processing system by clock control

Abstract: A repeat is performed in a computer system after detection of an error in the operation, the circumstances then being changed as much as possible. The clock frequency is then decreased by the selective blocking of a part of the clock pulses, so that second clock pulse cycles are produced which are composed of the same but wider spaced clock pulses. All functions remain possible duringthe second clock pulse cycles, be it at a lower speed. The circumstances can be further modified yet by first completely stopping the computer system for a given period of time, or by erasing the information sorted in a foreground store.

High rate digital modulation/demodulation method

Abstract: An electrical digital transmission method and circuits for improving recorded or transmitted information density. The embodiment serially modulates signal switching with a separation of at least two adjacent clock periods and not over eight clock periods in any sequence of byte transmissions. A fixed length transmission per byte is used. A serial clock cycle is provided per data byte and may be divided into two clock cycle sections. The first clock period of each section is not available for information modulation switching. The remaining clock periods of each section are available to contain electrical current switchings to encode a part of an information byte by permuting the switchings while maintaining the required switching separation. The first clock period of each section contains a switching only if no information induced switching occurs in its adjacent clock periods. These clock switchings assure an output switching within a maximum number of clock periods equal to the longest of the two sections.

Two level volume control for clock radio and the like

Abstract: A circuit arrangement is provided for obtaining two volume levels for clock radios. One volume level is for providing a soft volume during an initial slumber period of the clock radio when it is intended that persons go to sleep, and the other volume level is a loud volume during a wake-up period when it is intended that persons are to be awakened from their sleep. The two level volume control includes a latching circuit which has one of the components thereof arranged to be a switching element which is activated for changing the volume control of the clock radio to a lower volume during a slumber period. When the clock radio is deenergized by turning off the automatic timer switch the latching is also deenergized. When the clock radio is again energized by means of the conventional clock operated on-off switch the latching circuit remains deenergized thus causing automatic deenergization of the switching element automatically to increase the volume produced by the radio during a radio alarm period.

Switching circuit for power supply to electronic apparatus

Abstract: A switching circuit for the power supply of electronic apparatus, such as a radio, which includes a pair of flip-flop circuits, a clock set time switch for turning the apparatus on once every 24 hours for a short period of time, a sleep time switch which may keep the apparatus on for a short period of time without interfering with the functioning of the clock set time switch, a change of mode switch which may change the apparatus at any time from an on-state to an off-state or vice versa, and a disabling switch for the clock switch circuit.

Multi-channel digital clock

Abstract: Multi-channel digital clock for aircrart in which clock pulses are generated at a predetermined rate and applied to three independently controlled counters to determine different times such as real or clock time, flight time and elapsed time. The outputs of the counters are applied to a digital display by means of logic gates, and the time to be displayed is selected by a small single pole switch and an additional gate. The counts are transferred to the display on a time sharing basis which substantially reduces the number of lines required for the purpose. Operating power is normally supplied to the clock from an external source, and a battery is provided for supplying power to low power circuits such as the pulse source and counters to keep them running in the absence of external power. Switch operated means is provided for doubling the rate of the pulses applied to the real time counter or interrupting the application of pulses whereby the counter can be set up or down. Reset signals are applied to the flight time counter through a logic gate which prevents this counter from being reset while the aircraft is in operation. The elapsed time counter can be started, stopped and reset as desired.

Synchronized image intensifier gating

Abstract: An image intensifier gating device utilizing a stable high frequency clock, digital counting circuit, memory, subtractor, comparator and control logic to predict a next pulse in a regular pulse train; and a delay switch to account for the delays in the system to provide a gating signal in sufficient time to activate the gate and observe the next pulse.