Showing papers on "Clock gating published in 1977"

Circuitry for reducing power dissipation in equipment which operates in synchronism with clock pulses

Abstract: A minimum number of clock pulses required for keeping an electronic component in a waiting condition or state are intermittently applied to the electronic component, thereby minimizing the heat dissipation thereof. A control circuit, utilized in the invention, provides an output signal which permits continuous clock signals to be applied, for example, to memory chips, during read and write periods, but such control circuit reduces the number of clock signals applied to the memory chips during periods when the read and write processes are not required.

Asynchronous validity checking system and method for monitoring clock signals on separate electrical conductors

Abstract: An asynchronous validity checking system and method is disclosed for monitoring a plurality of clock signals carried on separate electrical conductors to assure continuing transitions of each clock signal. A master clock is utilized to produce a plurality of phase-related clock signals on the separate electrical conductors, and the transitions of the clock signals are sensed on each electrical conductor adjacent to the distribution point to a controlled unit to assure that all clock signals are continuously operational. The validity checking system includes a locking synchronizer having a plurality of flip-flops each of which receives a different one of the clock signals and a timing signal from a timing oscillator that is independent of, and asynchronous with respect to, the clock signals from the master oscillator with the clock signals being locked into the flip-flops on the rising leading edges of the pulses of the timing signal. A sequence and presence checking unit receives the output signals from the flip-flops and produces reset pulses which are coupled to digital counters incremented by the falling trailing edges of counter clock pulses that are frequency related to the timing signal pulses coupled to the locking synchronizer. As long as transitions of the clock signals are sensed on each of the electrical conductors to reset the counters within a predetermined period of time, no fault indication is produced. If a transition is not sensed, however, the counters are not reset within the predetermined period of time and a fault indication is produced that is indicative of a defect in a clock signal. Upon sensing of the failure of a transition of a clock signal, a fault indication is produced which may be utilized to automatically effectively stop the clock, selectively switch power off, or switch the master clock from a controlled unit, such as a magnetic recording device, to prevent damage and/or information loss.

Combined timekeeper and calculator with low power consumption features

Abstract: A combined timekeeper and calculator implemented on an LSI semiconductor chip includes a generator stage for generating basic clock signals and system clock signals which are obtainable by modifying the basic clock signals, and a processor stage responsive to the supply of the system clock signals for performing the operations required for the timekeeper mode and calculator mode. The basic clock signals also are modified to create second signals useful in the timekeeper mode. The generator to supply the processor unit with the system clock signals while the second signal is being generated. Upon completing the operations by the processor unit, a clock control circuit prevents the processor unit from being supplied with the system clock signals.

Remote control system for selective load switching, specifically for automotive vehicles

Abstract: A central station is connected to a ring bus system to which a number of separately addressable loads are connected through specific load receivers. The central station has a switching system by operation of selected switches of which, specific loads can be addressed. The ring bus system has a power line or bus, a clock line or bus, and a control line or bus. The clock line provides clock pulses during a selection cycle, and upon coincidence of a clock pulse with a pulse on the control bus, a specific load associated with a predetermined numbered pulse on the clock line can be addressed by sensing coincidence of the pulse on the control line and on the clock line. To separate selection cycles, a control signal is transmitted which may form a pause of clock pulses on the clock line. This control signal, in accordance with the invention, is represented by a series of pulses transmitted on a line other than the clock line, for example on the control bus. It is generated by a pulse generator in the central station to supply a predetermined number of such pulses on the control line only. The receivers have suitable receiver counters which respond to these pulses. Logic circuitry can distinguish between the selection pulses, which will have coincidence on the clock bus and on the control bus, and clock pulses which will appear only on the clock bus. The synchronization pulses are of a predetermined number which will appear only on the control bus so that the respective function synchronization counters in the central station and in the receiver will be synchronized anew for each selection cycle by digital evaluation of the function synchronization pulses.

Clock driven voltage comparator employing master-slave configuration

Abstract: A pair of clock driven voltage comparators are arranged in a master-slave configuration so that voltage comparisons are made only on a clock edge and the output is held valid over the entire clock period. Each comparator stage includes a latch to lock the comparator output in the logical state it was in when the latch was enabled.

High resolution auto-zero circuit for analog-to-digital converter

Abstract: An analog-to-digital converter includes an integrator which includes an amplifier having an offset voltage. A counter is responsive to a counter clock signal for counting during the duration of a first integration and transferring its count at the end of the first integration to a storage circuit. The counter is then reset. It then counts during the duration of a second integration. Coincidence circuitry is provided which causes the counter to be reset during the second integration when its count matches the count stored in the storage circuit. The counter then continues counting until the end of the second integration. The uncertainty associated with the count stored in the counter at the end of the second integration is improved by provision of a circuit responsive to the comparison signal and first and second clock signals for producing the counter clock signal. The counter clock signal is produced such that it is in phase with the first clock signal if the comparison signal at the end of the first integration occurred before the beginning of a subsequent pulse of the second clock signal. Otherwise, the third clock signal is delayed so that it is temporarily in phase with the second clock signal.

Electronic clock radio having nap/sleep feature

Abstract: An electronic clock radio using a clock integrated circuit and a radio integrated circuit. A first energizing potential when applied to the NAP/SLEEP input connection of the clock circuit, causes the clock circuit to switch from a first electric state to a second electric state. After a selected interval of time, not greater than 60 minutes, the clock circuit switches from the second electric state to the first electric state. The radio, normally in an OFF state is placed in an ON state only upon receiving a second energizing potential applied to its input connection. A control circuit, having a manually operable switch with NAP and SLEEP positions and being responsive to the electric states of the clock circuit, connects this second energizing potential to the radio input only when: (i) the manually operable switch is in the NAP position and the clock circuit is the first electric state, or (ii) the manually operable switch is in the SLEEP position and the clock circuit is in the second electric state.

64 Stage BCD (Bulk Charge-Transfer Device) Analog Memory with Differential Integrated Clock Pulse Generator

Abstract: A 64 stage BCD (Bulk Charge-transfer Device) with a new differential integrated clock pulse generator is developed. The device effectively eliminates problems of interference from external clock pulse circuits to a picture tube, and of output voltage variation in varying clock pulse frequency of a conventional device. The BCD consists of two clock pulse circuits fabricated differentially to drive two arrays separately. Experimental results show good matching of the two arrays. In addition, the device requires only one TTL level master pulse and two power supplies, thus enhancing its application to practical video delay lines.