Showing papers on "Clock gating published in 1983"

Variable frequency microprocessor clock generator

Abstract: A microprocessor based system (10) includes a central processing unit (CPU) (12) that controls the operation of a display (20) through a controller (22). System storage is provided with a read only memory (16) and random access memory (14). A reference clock signal is generated by a clock generator (26) which is input to a clock control circuit (24). The control circuit (24) generates a CLK signal that is connected to the clock input of the CPU (12). The control circuit (24) is operable to reduce the rate of the clock input to the CPU (12) when accessing the controller (22) which has a slower speed of operation than the random access memory (14). The control circuit (24) includes a programmable counter (38) for generating a gating signal after counting a predetermined number of cycles of the reference clock signal and initiating a count cycle only after generation of the gating signal. Generation of the gating signal by the counter (38) causes a latch circuit (68) to become transparent during selected transitions of the CLK signal. The control circuit (24) also provides for overriding the programmable counter (38) via an event counter circuit (56) which is effective to generate the gating signal independently of the programmable counter (38) after counting a predetermined number of count cycles of the programmable counter (38). The control circuit (24) is thereby effective to reduce the rate of the CLK signal as input to the CPU (12) and to retain the reduced rate of the CLK signal for a time period sufficient for the CPU (12) to access peripheral devices of low operating speed. Thus, the CPU (12) is able to control peripheral devices that have different maximum rates of operation.

Digital PLL decoder

Abstract: A digital PLL technique to provide an effective sampling interval and resolution shorter than the driver clock period. A multi-phase driver clock provides a clock signals phase-offset from each other. One clock output signal is used as the driver clock to clock an input sampler. A pattern of bit samples before, nominally at, and after a predicted clock edge indicates whether a leading or lagging phase should be substituted for the present driver clock signal. The phase difference is substantially less than the period of the fastest clock presently available to generate satisfactory shaped pulses.

Synchronizing large VLSI processor arrays

Abstract: Highly parallel VLSI computing structures consist of many processing elements operating simultaneously. In order for such processing elements to communicate among themselves, some provision must be made for synchronization of data transfer. The simplest means of synchronization is the use of a global clock. Unfortunately, large clocked systems can be difficult to implement because of the inevitable problem of clock skews and delays, which can be especially acute in VLSI systems as feature sizes shrink. For the near term, good engineering and technology improvements can be expected to maintain the feasibility of clocking in such systems; however, clock distribution problems crop up in any technology as systems grow. An alternative means of enforcing necessary synchronization is the use of self-timed, asynchronous schemes, at the cost of increased design complexity and hardware cost. Realizing that different circumstances call for different synchronization methods, this paper provides a spectrum of synchronization models; based on the assumptions made for each model, theoretical lower bounds on clock skew are derived, and appropriate or best-possible synchronization schemes for large processor arrays are proposed. One set of models is based on assumptions that allow the use of a pipelined clocking scheme, where more than one clock event is propagated at a time. In this case, it is shown that even assuming that physical variations along clock lines can produce skews between wires of the same length, any one-dimensional processor array can be correctly synchronized by a global pipelined clock while enjoying desirable properties such as modularity, expandability and robustness. This result cannot be extended to two-dimensional arrays, however—the paper shows that under this assumption, it is impossible to run a clock such that the maximum clock skew between two communicating cells will be bounded by a constant as systems grow. For such cases or where pipelined clocking is unworkable, a synchronization scheme incorporating both clocked and “asynchronous” elements is proposed.

Clock pulse signal generator system

Abstract: A clock pulse generator system for providing a highly stable clock signal consists of two separate redundant clock signal generators which are controlled to operate in dead synchronization with each other. A microprocessor controlled digital phase lock loop operates to control each of the two clock signal generators and selects among a plurality of operating states such that the average dynamic phase difference in the two clock pulse signals generated is practically zero. Furthermore, the instantaneous dynamic phase difference does not exceed the phase noise of the voltage controlled crystal oscillators of the phase lock loops and, in one embodiment, is normally less than ten pico seconds, each phase lock loop comprising means for performing a fine, as well as coarse, phase comparison among internally or externally generated reference signals, only one of which is the highly stable clock signal output.

Clock source with automatic duty cycle correction

Abstract: A clock source for timing and synchronizing the operation of digital data processing equipment and having automatic duty cycle correction is described A source of signals provides clock signals at a predetermined frequency A buffer circuit provides the true and complement clock signals to low pass filters that function to filter the true and complement clock signals to DC levels proportional to the duty cycle of the source signals The DC voltages represent instantaneous deviation voltages from a known reference and are applied to a differential amplifier circuit for providing a feedback signal for adjusting the duty cycle of the clock output pulses that are available One embodiment has the source of signals directly coupled to the buffer circuitry and utilizes the feedback signal to adjust the duty cycle of the signal source circuitry A second embodiment has the source signals capacitively coupled to the self-correcting circuitry and the feedback signals adjust the duty cycle of the clock output signal

Clock recovery arrangement

Abstract: A clock recovery arrangement particularly suitable for recovering a clock signal from Manchester-encoded data. The system includes a locally generated clock at twice the data rate. This locally generated clock is phase locked to the incoming data transitions. Then, the locked locally generated clock is divided by two to produce a clock signal corresponding to the data rate. A clock flipper circuit operating according to a predetermined algorithm determines whether to change the polarity of the clock signal to provide a correct polarity recovered clock.

Clock generating circuit providing a boosted clock signal

Abstract: A clock generating circuit includes a switch control circuit controlling a C-MOS circuit including first and second transistors having first and second conductivity types, respectively. Also included in the clock generating circuit is a bootstrap capacitor having a first end connected to the junction between the first and second transistors. The switch circuit includes a third transistor, having the first conductivity type, connected between the gate of the first transistor and the junction between the first and second transistors, and a fourth transistor, having the second conductivity type, connected between the gates of the first and second transistors. The gate of the second transistor is connected to receive an input clock signal and the gates of the third and fourth transistors are connected together to receive a delayed clock signal produced by delaying the input clock signal. The second end of the bootstrap capacitor is connected to receive a further delayed and inverted clock signal. When the delayed clock signal has a first value, the switching circuit connects the gates of the first and second transistors together and an output signal with a first level is produced at the junction of the first and second transistors. When the delayed clock signal reaches a second level, the switching circuit connnects the gate of the first transistor to the junction of the first and second transistors and the bootstrap capacitor boosts the output signal to a second level.

Fault testing a clock distribution network

Abstract: A method and apparatus for fault testing a clock distribution network which provides a plurality of clock signal lines to the logic networks which comprise a data processor. The fault testing apparatus includes a decoder for selecting one of the clock signal lines to be tested, and a test latch which is clocked by the selected clock signal line. The selected clock signal line is tested by setting the test latch to a first logic value (e.g., binary ZERO) and maintaining a second logic value (e.g., binary ONE) at the test latch input. If the second logic value is stored in the test latch when the clock distribution network is inhibited, then a stuck-on fault is indicated for the selected clock signal line. If the second logic value fails to be stored in the test latch when the clock distribution network is enabled, then a stuck-off fault is indicated for the selected clock signal line. Each clock signal line in the clock distribution network may be tested in this manner.

4-Phase clock generator

Abstract: A 4-phase clock generator comprises four gates for generating four clock signals from a master clock signal. The logic levels of four clock signals change in predetermined order after the master clock signal changes from a first logic level to a second logic level and they change in inverse order after the master clock signal changes back to the first logic level. The four clock signals are suitable to operate a shift register without making the adjoining transfer gates of the shift register conductive simultaneously.

Master/slave clock system

Abstract: A master/slave clock system including a slave clock configured for inexpensive and reliable control from the master. Each slave clock has an unregulated d-c supply adapted to be supplied with a-c power from the master clock. Threshold switching means in each slave clock is coupled across the d-c supply to sense an abnormally low d-c voltage level intentionally created by lowering the a-c supply level from the master. The threshold switching means switches the clock from the normal operating mode to the set mode where time is incremented at a predetermined rate for a duration controlled by the master clock in order to controllably set all slave clocks in the system to the correct time of day. The system conveniently allows all slaves to be reset to the same time when time is reset at the master, provides for automatic recovery after power failures, and provides a convenient means for automatically resynchronizing all slave clocks twice a day.

Prioritized clock selection circuit

Abstract: A clock selection circuit which selects and enables one of a plurality of clock circuits in response to initialization by a processing unit or detection of failure of an on-line clock circuit. The clock circuits are selected on the basis of a priority arrangement. The clock circuit failure is detected by a retriggerable monostable multivibrator and the selection priority is based on time delays generated by programmed counters associated with each clock circuit.

Power MOSFET transfer switch

Abstract: A switching circuit in a power supply for switching between a main power source and a standby power source includes gating device operated at the time failure of the main power source occurs to disable the operation of a plurality of MOSFETs which are switched by high frequency clock signals to couple the main power source to a load. When the main power source returns, the gating device switches the MOSFETs in synchronization with the power signals supplied by the main power source. The circuit includes a transformer operated by the high frequency clock signals to switch the MOSFETs, enabling the transfer of the power signals from the main source to the standby source to occur at the time the main power source fails.

Electronic controller for use with a surgical laser system

Abstract: The present invention is an electronic controller for use with a laser system which includes a mechanical triggering device and which generates a beam of light energy in the infrared spectrum The electronic controller includes a laser modulator which turns the laser system on and off at a frequency rate of two hundred cycles per second and a trigger/reset circuit which is electrically coupled to the mechanical triggering circuit The trigger/reset circuit provides a trigger signal in its triggered state and a reset signal in its untriggered state The electronic controller also includes a clock circuit which is electrically coupled to the triggering circuit and which provides clock signals in response to the trigger signal and a one-shot monostable, multivibrator circuit having an RC timing circuit which is electrically coupled to the clock circuit and which controls the pulse width of its output signal in a range of 0005 seconds and 01 seconds in response to the clock signals The electronic controller further includes a counter which is electrically coupled to the one-shot monostable, multivibrator circuit and which counts each of the clock signals and a comparator which is electrically coupled to the counter in order to compare the number of the counted clock signals to a selected number and to the clock circuit and which is electrically coupled to the clock circuit, so that, when the number of the counted clock signal equals said selected number, the comparator provides a clock inhibit signal in order to inhibit the clock circuit from providing any more clock signals

Clock monitor circuit and method

Abstract: A clock monitor circuit and method for providing an indication at the output thereof of the presence of an input clocking signal. If the clock input is operating properly, two charge storage nodes will be charged and the output of the circuit will be high. If the clock input is stuck, the output of the clock monitor circuit will be low.

Clocks and the performance of synchronisers

Abstract: The performance of two synchronisation schemes is compared. One scheme uses a fixed-period clock with the allowable resolution time of the synchronising flip-flop being one clock period, the other scheme uses a clock with extensible clock-pulse recurrence time and a special flip-flop with an additional output, M, which is asserted whenever the flip-flop is in the metastable state. By asserting the PAUSE input to the clock, clock-pulse generation is inhibited. The M outputs of the rank of flip-flops are collectively ORed to drive the PAUSE input of the clock, thus pausing clock-pulse generation when one or more of them is in the metastable state. A system using the first scheme fails when conflicting actions are taken by its components, owing to inconsistent interpretation of the outputs of the flip-flops that are in the metastable state. In the second scheme, a system fails when the job execution time exceeds a specified upper bound, owing to extension in clock pulse recurrence times. If the path delays from the M outputs to the PAUSE input of the pausable clock are small, the second scheme performs better. However, its performance degrades exponentially as the delays increase.

Radio controlled analogue clock

Abstract: The arrangement according to the invention serves for displaying radio clock time using mechanical hands, and consists of a combination of an electronic radio clock, electromechanical analogue clock and digital memory with non-volatile storage, in which the clock pulses coming from the electronic radio clock are constrained to be fed, e.g., in a series circuit, both to the memory and to the analogue clock, so that the memory contents always correspond with the hand position. Upon switching on, or after a power failure, the radio clock time no longer corresponds to the time indicated by the analogue clock. According to the invention, the radio clock time is continually compared electronically with the memory time, and as long as the two differ from one another clock pulses of a higher frequency are generated until the radio clock time once again corresponds with the memory time. In this way, the automatically running analogue clock also receives the correct radio clock time after a relatively short correction phase.

Counter circuit having improved output response

Abstract: An improved clock circuit in which a counter can begin its counting operation following the release of the reset signal always within one-half of the period of the input clock signal. The input clock signal is applied through a D-type flip-flop to one input of an exclusive-OR gate, and to the other input of the exclusive-OR gate directly. The output of the exclusive-OR gate drives the clock input to the counter. The clock input to the D-type flip-flop is supplied by the reset signal.

Time Measurement with a Multiphase Clock

Abstract: A multiphase clock is used to measure time intervals. The scheme consists of a main counter and digital verniers for start and stop. The system time resolution is limited by the intrinsic resolving time of the circuits rather than the clock rate. A 7 phase clock of ~28.57 MHz can measure time to 2.5 nsec accuracy with T2L type circuits.

Plasma coupled type device driving circuit

Abstract: PURPOSE:To increase the width of a clock pulse voltage which can be transferred by a method wherein a current restricting resistor is connected between a clock pulse supply source and the clock pulse input terminal, and, in addition to the input terminal, at least one or more of current sources are provided. CONSTITUTION:The current restricting resistor 1 is connected between clock pulse supply source 2 and the titled device 3, and, in addition thereto, the emitter of an NP- transistor Q1 is connected to said terminal of the device 3 via a resistor R1. Power sources V2 and V1 are kept connected to the base and the collector of the transistor Q1, respectively. When constructed in such a manner, since a stationary current is supplied from the transistor Q1, clock line current reduces on the decreasing the clock voltage, and the voltage which determines the lower limit the clock pulse which can be transferred increases. Therefore, the conventional defect such that the lower limit of the transferrable clock pulse region rises is alleviated.

Clock generator configuration for a redundant control system

Abstract: In this control system, one clock generator is in each case allocated to one control channel. The clock signals at the output of the clock generators are reliably synchronised with one another, each clock generator exhibits a number of delay sections (TV1...TVk-1) which are connected in series with one another to the output of an oscillator (O). Depending on a comparison between the clock signals (SA1...SAm) (system clocks), the output signal (SO...Sk-1) of the delay section (TV1...TVk-1) is in each case selected as clock signal (system clock) which is in phase with the other clock signals of the respective other control channels. The invention is mainly applicable to protected process computer arrangements.

Low power clock generator

Abstract: A clock generator circuit for producing with very little power dissipation an output clock signal having levels determined by positive and negative power supply levels from an input clock signal having levels determined by the positive power supply level and ground. In a low state of the input clock signal, an upper or first transistor of an output transistor pair connected in series between positive and negative power supply levels is turned off by applying a ground level to the base thereof, while the lower or second transistor of the output transistor pair is turned off by applying a positive potential to its base. When the input clock signal makes a transition from the low state to the high state, a bootstrap capacitor is charged between the positive and negative power supply levels to provide a boosted positive voltage to turn on the upper transistor. While the bootstrap capacitor is charging, the base of the lower transistor is lightly grounded to partially turn it on. When the charge on the bootstrap capacitor has reached a predetermined level, the base of the first transistor is taken to the negative power supply level through an inverting transistor, the base of which also receives the boosted voltage developed across the bootstrap capacitor. By using a fully dynamic circuit arrangement, only a very small amount of power is required for operating the circuit.

Memory driving circuit

Abstract: PURPOSE:To prevent storage information from damage due to the lack of the pulse width of an access clock by driving a dynamic RAM by using an OR signal between a pulse signal with prescribed width and a delay clock signal as an access clock. CONSTITUTION:A pulse B with the prescribed width is outputted from a pulse generating circuit 1 in accordance with a clock signal CS. The pulse B and the signal CS through a delay circuit 2 are applied to a NOR circuit NOR, a signal CS with wide clock width is formed by OR processing and the dynamic RAM3 is accessed by using the CS' as an access clock. Even if the pulse width of the clock CS is narrow, the storage information can be prevented from damage due to the lack of the pulse width of the access clock by the access clock CS'.

Clock extraction circuit for a PCM signal

Abstract: A clock extraction circuit for PCM NRZ signals which delivers substantially constant power and comprising at least one energy storage device charged by a constant current and discharged into a full wave amplifying circuit, the amplifying circuit delivering power to a filter which filters out the clock signal. This arrangement uses a passive tank circuit and ensures the clock signal from the NRZ data does not die out during periods of little or no clock content in the data stream.

Multi-system synchronizing device

Abstract: PURPOSE:To ensure the overall synchronization of systems and at the same time to attain synchronizing operation of a system as long as just one of processors is nondefective, by defining one of clocks which are owned properyly by plural processors respectively as a system shared clock. CONSTITUTION:A clock signal 28 produced by a clock generating circuit 21 is supplied to a counter 22, and to a clock feed line 10 through a buffer gate 26. While the output of the counter 22 is supplied to a comparator 23. If the coincidence is obtained between this output and the set value 24 which is proper to each of plural processors, a coincidence signal 29 is delivered. This signal 29 triggers a one-shot multivibrator 25, and the gate 26 of the clock 28 is opened by the output of the multivibrator 25. The output of the comparator 23 is also delivered to a shared clock setting line 11 to reset the counter 22 which is provided in each of those processors.

Clock signal generator for start-stop operation.

Abstract: The invention relates to a clock signal generator for start/stop operation with selectable mark-space ratio. The basic element of the clock signal generator is a band-filter-coupled oscillator having two inverting logic elements which is synchronised by a crystal oscillator for increasing the frequency stability. To improve the stability of the pulse lengths of clock pulses which are shorter than half a clock period, an additional crystal-controlled control oscillator is provided.