Showing papers on "Core router published in 2022"

A Novel Routing Strategy Towards Achieving Ultra-Low End-to-End Latency in 6G Networks

Abstract: Compared to 5G, 6G networks will demand even more ambitious reduction in endto-end latency for packet communication. Recent attempts at breaking the barrier of end-to-end millisecond latencies have focused on re-engineering networks using a hybrid approach consisting of an optical-fiber based backbone network architecture coupled with high-speed wireless networks to connect end-devices to the backbone network. In our approach, a wide area network (WAN) is considered with a high-speed optical fiber grid network as its backbone. After messages from a source node enter the backbone network through a local wireless network, these are delivered very fast to an access point in the backbone network closest to the destination node, followed by its transfer to the local wireless network for delivery to the destination node. We propose a novel routing strategy which is based on distributing the messages in the network in such a way that the average queuing delay of the messages through the backbone network is minimized, and also the route discovery time at each router in the backbone network is drastically reduced. Also, multiple messages destined towards a particular destination router in the backbone network are packed together to form a mailbag, allowing further reductions in processing overheads at intermediate routers and pipelining of mailbag formation and route discovery operations in each router. The performance of the proposed approach green based on these ideas has been theoretically analyzed and then simulated using the ns-3 simulator. Our results show that the average end-to-end latency is less than 380 µs (with only 46-79 µs within the backbone network under varying traffic conditions) for a 1 KB packet size, when using a 500 Gbps optical fiber based backbone network laid over a 15 Km × 15 Km area, a 50 Mbps uplink channel from the source to the backbone network, and a 1 Gbps downlink channel from the backbone network to the destination. The significant reduction in end-to-end latency as compared to existing routing solutions clearly demonstrates the potential of our proposed routing strategy for meeting the ultra-low latency requirements of current 5G and future 6G networks, particularly for mobile edge computing (MEC) application scenarios.

Estimation of Power Consumption in a Network-on-Chip Router

Abstract: Network-on-Chip is responsible for on-chip communication in multi-core and many-core processors. A Network-on-chip is composed of several routers and channels, each router working on behalf of a processor core or main memory. Buffers, switches, arbiters and allocators are some of the components inside the router of an on-chip network. Along with latency and throughput, power consumed by the interconnection network is a crucial factor to estimate the performance of a processor. In this paper we present a review of power consumption of Network-on-Chip router and its internal components. The majority of the power consumed by a Network-on-Chip router is consumed by the buffers.

An Efficient Cooperative Caching with Request Forwarding Strategy in Information-Centric Networking

Abstract: Information-centric network emphasizes on translating the current Internet paradigm from host driven to content driven. A numerous data-centric features like content driven routing, random network topology, and pervasive caching make ICN caching distinct from state of the art of work. This paper emphasizes on the cooperative caching in ICN and contributes a dominating-set-oriented cooperative caching strategy. It considers placement of data and request message forwarding in a strong co-relation. Here, the concept of connected dominating set has been used to create a virtual backbone that includes core routers where most popular content can be cached. The betweenness centrality parameter of that core router helps the routing strategy to forward request packet to the node where content is most likely to be stored which leads to faster retrieval of data. The proposed strategy will improve the performance parameters like content retrieval latency, cache hit ratio, mean hop distance, total transportation cost, and network overhead. The paper also discusses the working of proposed strategy with related algorithms, illustrations, and its benefits over state-of-the-art research in context of network performance.

Design and Verification of 1X5 ROUTER

Abstract: A router is a device that forwards the data packets along with the networks, commonly two LANs or WANs. It is an Open Systems Interconnection (OSI) layer 3 routing device. Depending on the address content in the incoming packets, this router routes a packet to an output channel. The packet has 3 parts, namely Header, payload and parity. In this project, a router of packet width 8 bits, payload length ranging from 1 byte to 31 bytes is implemented. This design is implemented in Verilog, verification is done using Universal Verification Methodology (UVM) and QuestaSim is used for functional coverage. This router consists of 4 submodules, namely First In First Out (FIFO), registers, Synchronizer and Finite State Machine (FSM). Five FIFOs are employed here and the final top module design is simulated and synthesized. The advantage of this router design is that it can receive only one packet at a time but five packets can be read out simultaneously.

Implementation of Dynamic and Efficient Virtual Channel Router for Network on Chip with Virtual Channel Arbitration Reduction and Parallel Switch Allocation Unit

Abstract: — Network on chip (NoC) is a new method of interconnecting modules in system on chip (SoC). Now a day, it is believed that this new communication subsystem will replace the bus-based architecture and will become dominant in SoC design technology. The performance of NoC mainly depends on the router so it is considered as the crucial part in the NoC design. This paper describes the different factors which affect the NoC performance and provides solution to solve these problems. The proposed router has three architectural modifications which makes it dynamic and efficient as compare to generic virtual channel router. This paper introduced the dynamic buffer allocation scheme in which virtual channels and buffer slots are selected and allocated dynamically depending on the network traffic conditions in real time which in turn increases the throughput. In this paper, we have focused on optimizing the virtual channel arbitration (VA) unit design and switch allocation (SA) unit design as well as focusing the maximum utilization of buffer so that it will result in minimizing the latency, area and power. The source code of the router is written in VHDL hardware description language and the simulation and synthesizing the router is done in Xilinx ISE Design Suite 13.1. The parameters like area, frequency, delay, power, latency and throughput are calculated. The results of this modified virtual channel router are compared with the generic virtual channel router. Keywords—Intellectual Property (IP), Network on Chip (NoC), Network Interface (NI), Switch allocation (SA), System-on-Chip (SoC), Virtual channel (VC), Virtual channel arbitration (VA)

Overview of energy routers control strategies

Abstract: In order to solve the problem of effective utilization of renewable energy, energy Internet technology came into being. As the key equipment of the energy Internet, the research on energy routers is of great importance. This paper introduces the energy router from the aspects of structure and operation mode, and summarizes a general energy router structure. At the same time, the control strategies of the energy router are systematically discussed. In view of the complex and diverse control strategies of the current energy router, this paper summarizes the research status of energy router control strategies and discusses the control strategies according to different classification methods.

MUA-Router: Maximizing the Utility-of-Allocation for On-chip Pipelining Routers

Abstract: As an important pipeline stage in the router of Network-on-Chips, switch allocation assigns output ports to input ports and allows flits to transit through the switch without conflicts. Previous work designed efficient switch allocation strategies by maximizing the matching efficiency in time series. However, those works neglected the interaction between different router pipeline stages. In this article, we propose the concept of Utility-of-Allocation (UoA) to indicate the quality of allocation to be practically used in on-chip routers. We demonstrate that router pipelines can interact with each other, and the UoA can be maximized if the interaction between router pipelines is taken into consideration. Based on these observations, a novel class of routers, MUA-Router, is proposed to maximize the UoA through the collaborative design (co-design) between router pipelines. MUA-Router achieves this goal in two ways and accordingly implements two novel instance router architectures. In the first, MUA-Router improves the UoA by mitigating the impact of endpoint congestion in the switch allocation, and thus Eca-Router is proposed. Eca-Router achieves an endpoint-congestion-aware switch allocation through the co-design between routing computation and switch allocation. Based on Eca-Router, CoD-Router is proposed to feed back switch allocation information to routing computation stage to provide switch allocator with more conflict-free requests. Through the co-design between pipelines, MUA-Router significantly improves the efficiency of switch allocation and the performance of the entire network. Evaluation results show that our design can achieve significant performance improvement with moderate overheads.

Performance Enhancement of SoC with Five Port Router by Replacing APB Protocol

Abstract: A In today's technological development and the advancement in IC technology, a huge number of intellectual property (IP)cores can be consolidated onto a single chip. Due to this, communication between the IP cores becomes more difficult. To overcome the restriction of this communication, we introduce a technology called NETWORK ON CHIP(NoC). This is an on-chip packet-switched network with IP cores connected to the network via interfaces, and the packets are sent to their respective destination to a multi-chip routing path. A router is an essential component for NoC architecture. The design had to be done effectively to build a competitive NoC architecture. In this proposed work router can be designed using Verilog. It has stored a forward type of flow control round robin arbitration and deterministic XY routing. The essential parts for a router are FIFO, arbiter, and crossbar. The plan behind the five-port router is intended to be used with the FPGA design platform to test the functionality of the NoC on hardware. The outline of the router is designed through Verilog and simulated using zynq board 7000 series and verified using system Verilog, and its feasible model is also verified.

A Service Migration Strategy for Communication Networks

Abstract: The requirement for IT infrastructure is continually changing, and new solutions are being developed as a result. Here in this scenario, the existing is referred as an old router and proposed is referred to new router configuration as an illustrative example. Hence there is a need for migration. In this work, A detailed network service migration strategy has been discussed, presented, and realized over real time scenario. This migration strategy requires a detailed, step-by-step methodology. Planning migration steps with several phases is the next and most crucial step. Successful migration requires level of planning. Logically, we are configuring the ports while physically disconnecting the fiber from router a and patching it to router b. The next phase is documentation, which includes in service notification (ISN) and performance reports. We'll verify the new router's performance after the migration to see whether it has any delays or packet losses that are lower than those of router A.

IOT Network Automation Implementation in Router Configuration Handling

Abstract: Network Automation or network automation in terms is the process of automating the configuration, management, testing, deployment, and operation of physical and virtual devices in a network. Thus, in this study, we will discuss the design of an IoT-based system for handling router configurations. This IoT-based router handling system uses the Python programming language which will be used as a command source on the server as a router configuration control. This system can also remotely use a smartphone so that it can be seen whether the configuration is running or system error. With this IoT-based router handling system, it will be easier for engineers to remotely and configure routers and save time in the router configuration process.

RR-SFVP: Design of arbitration unit based on Round Robin method with Strong Fairness and Variable Priority for NoC Router

Abstract: Abstract Network on chip (NoC) is one of the communicative structures for multiple cores that has scalability. In designing the NoC micro-router architecture, the arbitration unit is very important due to its significant impact on performance, chip occupation level and NoC power consumption. In this paper, a router arbitration architecture is proposed with a combination of variable priority arbitration and Round Robin. In this architecture, arbitration examines the requests of other channels based on the Round Robin index after requesting the flit to exit the virtual channel in addition to checking the availability of the relevant virtual channel.The simulation results show that the architecture of the RR-SFVP arbitration unit compared to the standard RR method, is 13.7% smaller in area and has 5.7% less power consumption and 53.7% less critical path delay.

Crossbar Switch Arbitration with Traffic Control for NoC

Abstract: NoC is a network of computing cores (IP cores) for processing information and routers for transferring data between IP cores. NoC has a lot of applications: it is used in communications, transport, in the Internet of Things ecosystems and the Internet of Drones. Routers are used to efficiently exchange messages between IP cores. One of the important functions of a router is arbitration. In this paper, we review the main arbitrage methods: Fixed Priority Arbitrage (FPA), Matrix Arbitrage, Round Robin Arbitrage (RRA), and some of its modifications for crossbar switching systems. We propose a conceptual framework for traffic control of NoC routers using arbitration techniques. Fairness as an important property of an arbitrator is considered. Different approaches have been proposed and some have been justified. The comparison of the simulated data shows that the results are in good agreement with both available experimental data and proposed models in the literature.

Smart Agent and Modified Master-Backup Algorithm for Auto Switching Dynamic Host Configuration Protocol Relay through Wireless Router

Abstract: Several problems happened in a wireless router which is the number of clients that connected to DHCP (Dynamic Host Configuration Protocol) services and also durability in connectivity. Wireless router which is used in the office nowadays usually has a small memory and also CPU power. Memory or CPU sometimes could be running out when a wireless router does some background services. DHCP is one of the services needed to run in a wireless router. DHCP is interrupted when memory or CPU is full. DHCP relay and modification of the backup algorithm needed to overcome this situation when the memory or CPU in the wireless router is limited. The modification of the backup algorithm is a mechanism to switch the main router with the backup router when the main router memory is busy. DHCP relay could become a DHCP server directly when the main router is busy. Wireless router in another side could be formatted with open-source OS such as OpenWRT to become bridge interface that connected to DHCP relay. The scenario that tested in this research is using Cisco DHCP relay services in combination with OpenWRT wireless router, in variation with Mikrotik original “capsman” protocol with DHCP relay in combination with wireless-enabled Mikrotik and also in combination with OpenWRT wireless router. The result shows that OpenWRT in configuration with DHCP relay and backup algorithm could extend the number of a client connected, and also the durability of the wireless router runs its services as DHCP forwarder to DHCP relay and DHCP server. Theoretically, the number of the client that could connect in class C IPv4 address is 253 clients. Practically, in some wireless router brand, the number of the client is limited to 15 to 30 clients because that number is an optimal client for consuming the bandwidth. DHCP relay scenario could extend that limit to have a larger number of the client, and the new backup algorithm in combination also doesn’t decrease IP release time significantly from usual DHCP using a direct connection.

Design and Implementation of Smart Packet Processor for the Cognitive Packet Network Router

Abstract: As the Internet expands significantly in numbers of users, servers, IP addresses, and routers, the IP based network architecture must evolve and change. Recently, Cognitive Packet Networks (CPN) was proposed as an alternative packet network architecture, where there is no routing table, instead reinforcement learning (Random Neural Networks) is used to route smart packets [1,2]. CPN routes packets based on QoS, using measurements that are constantly collected by packets and deposited in mailboxes at routers. Previously, CPN is implemented in a software test-bed. In this paper, we present design approaches for CPN network processor chip. Particularly, we discuss implementation details for one of the modules in the chip: The smart packet processor; which includes a neural network hardware design.