Showing papers on "Decimal published in 1990"

How to print floating-point numbers accurately

Abstract: We present algorithms for accurately converting floating-point numbers to decimal representation. The key idea is to carry along with the computation an explicit representation of the required rounding accuracy.We begin with the simpler problem of converting fixed-point fractions. A modification of the well-known algorithm for radix-conversion of fixed-point fractions by multiplication explicitly determines when to terminate the conversion process; a variable number of digits are produced. The algorithm has these properties: No information is lost; the original fraction can be recovered from the output by rounding.No “garbage digits” are produced.The output is correctly rounded.It is never necessary to propagate carries on rounding.We then derive two algorithms for free-formal output of floating-point numbers. The first simply scales the given floating-point number to an appropriate fractional range and then applies the algorithm for fractions. This is quite fast and simple to code but has inaccuracies stemming from round-off errors and oversimplification. The second algorithm guarantees mathematical accuracy by using multiple-precision integer arithmetic and handling special cases. Both algorithms produce no more digits than necessary (intuitively, the “1.3 prints as 1.2999999” problem does not occur).Finally, we modify the free-format conversion algorithm for use in fixed-format applications. Information may be lost if the fixed format provides too few digit positions, but the output is always correctly rounded. On the other hand, no “garbage digits” are ever produced, even if the fixed format specifies too many digit positions (intuitively, the “4/3 prints as 1.333333328366279602” problem does not occur).

How to read floating point numbers accurately

Abstract: Consider the problem of converting decimal scientific notation for a number into the best binary floating point approximation to that number, for some fixed precision. This problem cannot be solved using arithmetic of any fixed precision. Hence the IEEE Standard for Binary Floating-Point Arithmetic does not require the result of such a conversion to be the best approximation.This paper presents an efficient algorithm that always finds the best approximation. The algorithm uses a few extra bits of precision to compute an IEEE-conforming approximation while testing an intermediate result to determine whether the approximation could be other than the best. If the approximation might not be the best, then the best approximation is determined by a few simple operations on multiple-precision integers, where the precision is determined by the input. When using 64 bits of precision to compute IEEE double precision results, the algorithm avoids higher-precision arithmetic over 99% of the time.The input problem considered by this paper is the inverse of an output problem considered by Steele and White: Given a binary floating point number, print a correctly rounded decimal representation of it using the smallest number of digits that will allow the number to be read without loss of accuracy. The Steele and White algorithm assumes that the input problem is solved; an imperfect solution to the input problem, as allowed by the IEEE standard and ubiquitous in current practice, defeats the purpose of their algorithm.

Communication system which uses characters that represent binary-coded decimal numbers

Abstract: A computer system which creates many styles of character sets whose characters represent either a group of five-bit or a group of eight-bit binary-coded decimal numbers. The character sets are used for common communication, other than handwriting, by people or machines, in any sensible medium. Having interchangeable eight-bit and five-bit character sets provides transparent interface between communication for people, and communication for technical and machine purposes. The purpose of this system is to create a single character set which will express all of the languages of the world. The system is comprised of three primary processes: designing, coding, and formatting the binary-coded decimal characters. When supplied with cleartext information, the system converts the information and expresses it with the created character set, in any sensible medium. It converts each character of the cleartext information to the corresponding character of the created character set. The invention provides a default mode to be operated as is, using preset programmed parametric and switch settings and a sample of clear text, to demonstrate typical operation and invite practice and extension to its full capability.

Fractional/decimal/digital converting calculator

Abstract: A Production Pal is provided that permits a user to perform calculations directly upon fractional data. Input to the Production Pal can be either a length expressed as a mixed fraction or rectangular measurements (length×width). The desired size, original size, and scaling factor (decimal or percent) are variables that can be manipulated. The circuit architecture employed utilizes a central processor unit, read only memory, random access memory, keyboard, and display. A fractional computation unit is a unique contribution. The keyboard contains numerous keys devoted to direct fractional keystroking. The scaling capabilities are also a unique contribution.

A new lower bound for the de Bruijn-Newman constant

Abstract: Strong numerical evidence is presented for a new lower bound for the so-called de Bruijn-Newman constant. This constant is related to the Riemann hypothesis. The new bound, ?5, is suggested by high-precision floatingpoint computations, with a mantissa of 250 decimal digits, of i) the coefficients of a so-called Jensen polynomial of degree 406, ii) the so-called Sturm sequence corresponding to this polynomial which implies that it has two complex zeros, and iii) the two complex zoros of this polynomial. Aproof of the new bound could be given if one would repeat the computations i) and iii) with a floatingpoint accuracy of at least 2600 decimal digits.

Acquiring meaning for decimal fraction symbols: A one year follow-up

Abstract: Fourth graders with differing achievement records participated in a specially designed two week unit on decimal fractions. Students were encouraged to connect meaningful referents with decimal fraction symbols and use these meanings to develop procedures for adding and subtracting decimal numbers. One year later these students and a matched set of fifth graders were interviewed and given paper-and-pencil tests. Three questions were of interest: (1) Do short term changes in the processes students use to solve problems remain stable over time; (2) Do students who have been instructed in conceptually-based processes exhibit a higher level of performance one year later than their conventionally taught peers; and (3) What is the relationship between entry achievement level and the year-long effects of conceptually-based instruction? The results suggest that: (1) If students used the meanings of written symbols as a basis for solving problems immediately after instruction, they used these processes to solve problems one year later, regardless of entering achievement; (2) Compared to their conventionally taught peers, students in the lower achievement group benefitted relatively more from the conceptually-based instruction than students in the higher achievement group; (3) However, higher achieving students were more likely to exhibit use of conceptually-oriented processes one year later than the lower achieving students.

Vector and Parallel Algorithms for Integer Factorisation

Abstract: The problem of finding the prime factors of large composite numbers is of practical importance since the advent of public key cryptosystems whose security depends on the presumed diculty of this problem. In recent years the best known integer factorisation algorithms have improved greatly. It is now routine to factor 60-decimal digit numbers, and possible to factor numbers of more than 110 decimal digits. We describe several integer factorisation algorithms, and consider their suitability for implementation on vector processors and parallel machines.

Zero warranty circuit for data path having different bit width from the length of packed decimal operand

Abstract: In a zero warranty circuit which checks the length of a packed decimal operand processed in a circuit having a bit width different from the length of the operand, the latter is translated into a sequence of bits corresponding respectively to different decimal digits of the operand. Each of the bits has a first value indicating validity of the corresponding decimal digit and a second value indicating invalidity of the corresponding decimal digit. Those of the bits which correspond to the decimal digits of odd numbered positions are inverted and applied to first coincidence gates for detecting a coincidence with a respective one of those of the bits which correspond to the decimal digits of even numbered positions. The presence of a nonzero bit in each of the decimal digits of even numbered positions is detected and supplied to second coincidence gates for detecting a coincidence with the output signals from the first coincidence gates to generate a signal indicating an exceptional event.

Binary to decimal, one more time

Abstract: In [1] Knuth presents an algorithm for converting a binary fraction to a decimal fraction that satisfies certain conditions. Knuth found the algorithm interesting not only because it was short and useful but because he could “see no way to demonstrate its correctness by conventional methods”. He hoped that “others with more experience in formal methods will agree that the algorithm is interesting and will help me figure out what I should have done.”.

A compact representation of hierarchical relations using decimal notations

Abstract: A decimal notation satisfies many simple mathematical properties. and it is a useful tool in the analysis of trees. A practical method is presented, that compresses the decimal codes while maintaining the fast determination of relations (e.g., ancestor, descendant, brother, etc.). A special node. called a kernel node,including many common subcodes of the other codes, is defined, and a compact data structure is presented using the kerne! nodes. Let n(m) be the number of the total (kernel) nodes. It is theoretically proved that encoding a decimal code is a constant time, that the worst-case time complexity of compressing the decimal codes is O(n+m 2), and that the size of the data structure is proportional to m. From the experimental results of some hierarchical semantic primitives for natural language processing, it is shown that the ratio m/n becomes an extremely small value, ranging from 0.047 to 0.13.

Primality testing and integer factorisation

Abstract: The problem of finding the prime factors of large composite numbers has always been of mathematical interest. With the advent of public key cryptosystems it is also of practical importance, because the security of some of these cryptosystems, such as the Rivest-Shamir-Adelman (RSA) system, depends on the difficulty of factoring the public keys. In recent years the best known integer factorisation algorithms have improved greatly, to the point where it is now easy to factor a 60-decimal digit number, and possible to factor numbers larger than 120 decimal digits, given the availability of enough computing power. We describe several recent algorithms for primality testing and factorisation, give examples of their use and outline some applications.

The normal integral

Abstract: ANORM is a reliable, portable Fortran function program, written in the style of the SPECFUN package for computing the normal probability distribution to full machine precision on most contemporary computers. The main computation evaluates near-minimax approximations that are theoretically accurate to at least 18 significant decimal digitals. Special care has been taken in implementation to minimize error contamination in the crucial computations of the exponential and to provide full accuracy in the computation with large negative arguments. ANORM returns 0.0 for arguments smaller than the machine-dependent constant XLOW and returns 1.0 for arguments greater than the machine-dependent constant XUPPR.

Numeral reading adding means for rule voice synthesizing device

Abstract: PURPOSE:To give correct reading at the time of a morpheme and to give the reading which can cope with general phoneme variation by registering all combinations of the numeral having phoneme variation which can not be handled according to the rule and auxiliary numeral previously in a dictionary as exceptional reading. CONSTITUTION:The device is provided with a means which changes fluctuations of various numerical expressions such as decimals, fractions, and round numbers and expressions using arithmetic numbers and Chinese character numbers to a standard form based upon the Chinese character numbers, analyzes the format of a document after the conversion to the standard form and divides the document into words, and generates the part of speech, reading, etc., of each word. Further, a means which handles variation in phoneme by the combination of a numeral and an auxiliary numeral is provided and all combinations of numeral and auxiliary numeral which can not handle the phoneme variation are regarded as exceptional reading according to the rule based upon the array of phonemes at the junction part between the numeral and auxiliary numeral and registered in the dictionary as one-digit words. Then correct reading is given at the time of the morphemic analysis, and standard reading which is not registered in the dictionary as exceptional reading to give the reading which handles general phoneme variation.

Multi-functional electronic desk calculator

Abstract: A multi-functional electronic desk calculator has numeral value keys for inputting a numeral value and a decimal point key for inputting a decimal point. The calculator also has a device for detecting depression of the numeral value keys to produce a first signal representative of being in a numeral value inputting mode, a device for detecting depression of the decimal point key to produce a second signal representative of input of the decimal point, a predetermined single key, and a device for operating the predetermined single key as a key used for inputting hexagesimal number when the first signal is produced and the second signal is not produced, and for operating the predetermined single key as a conversion key for performing conversion from decimal number to hexagesimal number when the first signal is not produced or when the second signal is produced.

Address setting device for terminal equipment for remote monitor control

Abstract: PURPOSE:To facilitate address setting by providing an input selection section selecting whether a specific address is entered by a key in a decimal number or in a hexadecimal number freely so as to freely convert data display and providing a data conversion section converting a specific address data into a binary number and sending the result. CONSTITUTION:Whether the key entry of a specific address is entered in a decimal number or in a hexadecimal number is set freely by the transmission reception of an optical wireless signal in an address setting device 11, and an input selection section is provided, which selects freely whether a specific address is entered by a key in a decimal number or in a hexadecimal number freely and converts data display freely, and a data conversion section is provided, which converts the inputted specific address data into a binary number and sends it. Thus, the specific address is set in a decimal number or in a hexadecimal number and the address is easily set without conversion of binary number.

Guarantee-of-zero circuit for a data path having a bit span differing from the length of a condensed decimal operand

Abstract: The circuit makes it possible to control the length of the processed operand, the latter being translated by a decoder (20) into a sequence of bits corresponding respectively to the various decimal digits of this operand, each bit having a first value indicating the validity of the corresponding decimal digit and a second value indicating the non-validity of the corresponding decimal digit. The bits corresponding to the decimal digits with odd-numbered place are inverted by invertors (22 to 25) and applied to first equivalence gates (26 to 29) so as to detect an equivalence with respective bits which correspond to the decimal digits with even-numbered place. The presence of a non-zero bit in each of the decimal digits with odd-numbered place is detected by absence-of-zero detectors (31 to 34) and provided to second equivalence gates (35 to 38) so as to detect an equivalence with the output signals from the first equivalence gates, so as to generate a signal indicating an exception event. … Application to data processors. … …

Method and device for calculating function value

Abstract: PURPOSE:To shorten the time required for a calculation by listing a function value within a range set in advance to a table, reading out the nearest function value, and also, executing an approximate operation based on the read-out function value and calculating an arbitrary function value. CONSTITUTION:By a decimal fraction part extracting part 1, a given angle X is multiplied by 1/2pi, and from a result of multiplication, only a decimal fraction part is fetched. Subsequently, the decimal fraction part converted 2 to a fixed decimal point format is shifted to the left by (n) - 1 bits, and an integral part and a decimal part are separated by a separating part 3. Next, by a sine value read-out control part 5, it is supplied to a sine value table memory 4 as a designated address, based on a head address of the sine value table memory 4 set in advance and a data size of a sine value and the integral part. Thereafter, based on a sine value, a cosine value and a shift angle which are read out of the sine value table memory 4, a sine value is calculated by a sine value calculating part 8. Subsequently, a sine value sinX is converted 9 to a floating decimal point format.

Circuit arrangement for decimal arithmetic

Abstract: A circuit for performing decimal subtraction at high speed has an execution time which is independent of the existence of a borrow condition. The subtraction circuit is particularly suited for use in microcoded computer circuits.

Interpolating method in image scan recording

Abstract: PURPOSE:To suppress the generation of interference nonuniformity due to interpolation generated at the time of performing the duplication of an original image by changing the interpolating position of data whose amount is decided by a variable power ratio at every one or several scanning lines. CONSTITUTION:Assuming the variable power ratio (m) as m=r+t (r is integer part of (m), t is decimal part of (m)), the integer part (r) is set as interpolation data even at the first position of a picture element in an interpolation table No.1. Next, the sum of the decimal part (t) and the (m) is assumed as A. The integer part of the A is set as the interpolation data at the next position of the picture element. And the sum of the decimal part of the A and the (m) is set as a new A. Such operation is repeated for the number of times equivalent to the number of picture elements comprising one scanning line. Next, No.2-No.4 interpolation tables are generated so that the same sequence of an interpolation data string is not attached on a No.1 interpolation table and among them mutually. When the variable power ratio (m) is set at a variable power setting apparatus 6, a CPU 7 generates four kinds of interpolation tables No.1-No.4, and writes them on a table memory 8.

Two-input logical operation system for addition or subtraction and decimal addition/subtraction system

Abstract: PURPOSE: To perform an arithmetic operation at high speed by selecting an m-ary predictor in accordance with a predictor selection signal generated at every digit as a result value of addition or subtraction corresponding to the relevant predictor selection signal. CONSTITUTION: Correction in accordance with the addition/subtraction is applied to each digit of first input numeric value data inputted being displayed in an n-ary e.g. hexadecimal method at a correction circuit 2 in accordance with each digit. Corrected first input numeric value data 16 is inputted to a spare value selection signal generation circuit 6 with second input numeric value data inputted being displayed in the hexadecimal method. The circuit 6 generates the predictor selection signal decided corresponding to inputted both input numeric value data. Simultaneously, m-ary predictors, for example, decimal predictors decided corresponding to the number of digits of the first and second input numeric value data inputted from a predictor generation circuit 4 can be generated. The decimal predictor is selected at a selection circuit 8 at every digit as the result value of the arithmetic operation of the addition or subtraction of the digit. In such a manner, no signal delay occurs in a re-correction circuit, which accelerates the arithmetic operation. COPYRIGHT: (C)1991,JPO&Japio

Method for converting floating point

Abstract: PURPOSE:To simplify a necessary processing for conversion by converting a floating point displaying form without the intermediary of the character data in which the data of a real number are displayed by the decimal system. CONSTITUTION:After the real number value by the floating number displaying of a first form expressed by the binary number of 32 bits, an index part and a mantissa part are respectively separately converted without the decimal character data, the conversion of the floating point displaying form from a first form to a second form is executed. Namely, the conversion of the index part is executed from the carry due to the remainder of the index part at the time of the function of 16 =(2 ) =2 ...(4) and the conversion from the binary to the sexadecimal of the mantissa part. Since for the mantissa part, the first form is displayed by the binary number and the second form is displayed by the sexadecimal number, the conversion is executed from the remainder of the index part when the conversion is executed from the binary to the sexadecimal together with a first form hidden bit. Thus, the conversion which keeps the accuracy of the real value before the conversion at the maximum can be performed.

Decimal alignment tab processing system of document preparing device

Abstract: PURPOSE:To easily prepare an attractive document by controlling a set decimal alignment tab position which an absolute coordinate position, storing the pitch of respective input characters, and developing number strings so that decimal points are set at the decimal alignment tab position. CONSTITUTION:The document preparing device consists of a keyboard 1 as an input device, a CRT display 2 which is a display device as an output device, a printer 32, the main body 4 of the document preparing device, and a disk device 5 incorporated in the main body 4. Here, when the decimal alignment tab position is set, it is controlled with the absolute coordinate position and the pitch of the respective input characters is stored; when a decimal point is inputted after a decimal tabulation code is inputted, its absolute coordinate position is calculated to determine the decimal alignment tab position, so that the number string is developed having its decimal point at the decimal alignments tab position. Consequently, even if the character pitch is changed optionally during document preparation, decimal alignments tab positions are aligned and the attractive document is easily prepared.

Floating point arithmetic processor

Abstract: PURPOSE: To shorten the required time by checking decimal and exponent results of floating-point processing in floating-point multiplication and addition/ subtraction to check whether normalization and rounding processing can be skipped or not and shortening the succeeding processing at the time when required conditions are satisfied. CONSTITUTION: A new function to discriminate whether normalization and rounding processing are requested or not is given to a control logic 11. When the operation processing is addition of two numbers of the same sign, subtraction between two numbers having different signs, or multiplication, the most significant bit of the resultant decimal is checked, and a normalization request is completely forecasted by the result to determine whether normalization is not necessary at all, it can be executed by one-bit left shift, or it can be executed by one-bit right shift. Decimal and exponent results are checked to discriminate whether rounding processing is required or not; and the result is transferred to a floating-point register 14 when normalization neither rounding processing is not necessary. Thus, steps of normalization processing and rounding processing can be skipped to increase the operation processing speed.

Pipeline type floating point adder/subtractor for digital computer

Abstract: PURPOSE: To compensate bit loss due to set bit discarding by providing a decimal part separation and array device, an exponential part adder, etc., and improving a subtracting method for two floatingpoint decimal numbers and generating a sticky bit signal. CONSTITUTION: Source operands 1 and 2 are outputted to a decimal-part 1 separation and array device 12, a decimal-part 2 separation and array device 13, etc., through latches 10 and 11 and the decimal parts are arrayed. In this case, the devices 12 and 13 generate sticky bit signals to compensate the discarding of set bits. Then one decimal part is subtracted and optionally specified through latches 16 and 17 and an exponential part adder 15, the complement of the specified decimal part is generated and added to the other decimal part, and the result is normalized by a normalizing device 18 and then sent to an exponential part adjusting device 19. The device 19 selects and adjusts a larger floating-point exponential part and sends the result to a rounding and combining device 21. The device 21 adds a rounding constant to the result of the device 19 to perform a rounding and combining process and outputs the result through a latch 22, so that the subtracting process is properly performed.

Image forming method

Abstract: PURPOSE:To attain a speedy picture element processing by expressing the numeric value such as the coordinates of a segment to compose a contour line in a virtual real number in which a decimal point is placed in a word and processing the value. CONSTITUTION:For respective data of the segment in a line storage device 1, as indicated in a figure, the virtual decimal point is placed in the midpoint in one word, the data such as the coordinates value of the segment are expressed as the virtual real number in which the left side and right side of the decimal point are made into an integer part and a decimal part, respectively, and they are processed. The left edge bit of the word is made into a code bit, and a negative number is expressed with the complement of 2 equal to the integer. The data in a scan line storage device 3 are also in the same expression. Thus, since the numeric value such as the coordinates of the segment is dealt with as the virtual real number, the most calculations in a scan conversion can be executed by an efficient integer calculation, the processing can be made high-speed, simultaneously, the coordinates value, etc., can be extended to a real number value without causing the increase of the processing time, and a degree of freedom is increased.

Display method for nc working program

Abstract: PURPOSE:To display an input address word on a display device in the same expression form as the address word inputted via a tape when the first address word is regenerat ed by preserving the number of zero existing at a data part for an address word consisting of the English and numeric character strings and storing the number of zero after the compression/conversion of them CONSTITUTION:An address word is taken out of an external memory and a data part is isolated A numeric character string of the data part has a prescribed format (002200Yen0) and is read at the head of the string The processing of this character string is through at a punctuation 'Yen0', A decimal part processing is performed with a decimal point; while the number of zero is increased with existence of '0' and the following one character is read In the decimal part processing, a character string is read at the rear part and the same procedure is continued until a decimal point or a character except '0' is read In a converted address word, an English charac ter code and the number of zero of the integer and decimal parts are shown in 8 and 4 bits respectively While a data part (2200) is shown in 32 bits Then the converted address word is outputted to the external memory As a result, the numerical strings 002 and 200 of the data part are compressed to 5 bytes Thus the data part of the address word is regenerated on a display device in the same form as that of an input state because the number of zero is stored