Showing papers on "Division (mathematics) published in 1991"

The General Theory of Integration

Abstract: Introduction and prerequisites Division systems and division spaces Generalized Riemann and variational integration in division systems and division spaces Limits under the integral sign, functions depending on a parameter Differentiation Cartesian products of a finite number of division systems (spaces) Integration in infinite-dimensional spaces Perron-type, Ward-type, and convergence-factor integrals Functional analysis and integration theory References

Bacterial Growth and Division: Biochemistry and Regulation of Prokaryotic and Eukaryotic Division Cycles

Abstract: Prologue. Bacterial Growth. A General Model of the Bacterial Division Cycle. Experimental Analysis of the Bacterial Division Cycle. Cytoplasm Synthesis during the Division Cycle. DNA Replication during the Bacterial Division Cycle. Synthesis of the Cell Surface during the Division Cycle. Density and Turgor during the Division Cycle. Variability of the Division Cycle. The Segregation of DNA and the Cell Surface. Transitions and the Bacterial Life Cycle. The Division Cycle of Caulobacter crescentus. Growth and Division of Streptococcus. Growth and Division of Bacillus. The Growth Law and Other Topics. The Eukaryotic Division Cycle. Conservation Laws of the Division Cycle. Epilogue. Bibliography. Author Index. Subject Index.

Cubic recursive division with bounded curvature

Abstract: Previous cubic recursive division schemes have had either zero or unbounded curvature at the singular points. This paper describes a formulation which gives bounded non-zero curvature and close to curvature continuity. Although it was claimed at the conference that this formulation was C2, this is not (quite) true.

Fractional n/m synthesis

Abstract: A frequency synthesizer employs a frequency divider (103) and a frequency multiplier (403) in the feedback loop. The minimum frequency separation between two adjacent synthesized channels is equal to the reference frequency divided by the multiplication ratio of the multiplier. The division ratio of the frequency divider (103), which can be analyzed as the sum of an integer and a fractional portion, is varied with time by a digital sequence, resulting in a minimum frequency increment equal to a fraction of the reference frequency. The multiplier (403) acts to reduce the nonlinearities of the frequency synthesizer when the fractional portion of the division ratio causes a large variation in the instantaneous division ratio by reducing the effective division ratio of the loop.

Digital cross connection apparatus

Abstract: A cross connection apparatus which performs cross connection using the divided VT signals, as cross connection units, obtained by division of the VT sizes foming virtual tributary (VT) signals of input side transmission line signals into whole integers by predetermined common size unit, wherein it is possible to perform cross connection by common hardware even if a plurality of types of VT signals having different VT sizes are input.

Integer division using reciprocals

Abstract: By using a reciprocal approximation, integer division can be synthesized from a multiply followed by a shift. Without carefully selecting the reciprocal, however, the quotient obtained often suffers from off-by-one errors, requiring a correction step. The author describes the design decisions made when designing integer division for a new 64-b machine. The result is a fast and economical scheme for computing both unsigned and signed integer quotients which guarantees an exact answer without any correction. The reciprocal computation is fast enough, with one table lookup and five multiplies, so that this scheme is competitive with a dedicated divider, while requiring much less hardware specific to division. The real strength of the proposed method is division by a constant, which takes only a single multiply and shift, one operation on the machine considered. The analysis shows that the computed quotient is always exact: no adjustment or correction is necessary. >

High-speed VLSI arithmetic processor architectures using hybrid number representation

Abstract: The design of high-speed architectures is addressed for fixed-point, two's-complement, bit-parallel, pipelined, multiplication, division and square-root operations. The architectures presented make use of hybrid number representations (i.e. the input and output numbers are presented using two's complement representation, and the internal numbers are represented using radix-2 redundant representation). A fast, new conversion scheme for converting radix-2 redundant numbers to two's-complement binary numbers is presented, and this is used to design a reduced latency bit-parallel multiplier. The novel sign-multiplexing scheme helps detect the sign of a redundant number very quickly and is used in combination with the remainder conditioning scheme to achieve very high speed in fixed-point division and square-root operators. These architectures require fewer pipelining latches than their conventional two's-complement counterparts. Reduction in latency without sacrificing clock speed has resulted in reduced computation time for these operations. >

Color liquid crystal display system

Abstract: PURPOSE:To make a color liquid crystal display on a black-and-white display transmission type liquid crystal panel in simple panel structure. CONSTITUTION:The black-and-white display transmission type liquid crystal panel 1 is divided into plural display areas (1)-(4), and groups L1, L2, L3, and L4 of color light sources corresponding to the colors of color image display data of the R, G, and B colors are arranged on the back surface of the liquid crystal panel 1 in the respective display areas. When the color image display data is selected, one by one, and sent to the liquid crystal panel 1 on a time- division basis, the color light sources in the groups L1, L2, L3, and L4 of the color light sources are selected corresponding to the colors of the selected color image display data, and the group of the light sources at the position corresponding to the display area on the liquid crystal panel 1 based upon the image display data is selected and made to illuminate. Consequently, the duty of the light source illumination is increased to suppress the transfer speed of the image display data to several times as high as that of the color display, and the color light sources and image display data are made coincident to display a color images with faithful colors.

Fast division using accurate quotient approximations to reduce the number of iterations

Abstract: A class of iterative integer division algorithms is presented based on lookup table Taylor-series approximations to the reciprocal. The algorithm iterates by using the reciprocal to find an approximate quotient and then subtracting the quotient multiplied by the divisor from the dividend to find a remaining dividend. Fast implementations can produce an average of either 14 or 27 b per iteration, depending on whether the basic or advanced version of this method is implemented. Detailed analyses are presented to support the claimed accuracy per iteration. Speed estimates using state-of-the-art ECL (emitted coupled logic) components show that this method is faster than the Newton-Raphson technique and can produce 53-b quotients of 53-b numbers in about 28 or 22 ns for the basic and advanced versions. >

A fast division algorithm for VLSI

Abstract: A novel and fast method for VLSI division is presented. The method is based on Svoboda's algorithm and uses the radix-2 signed-digit number system to give a divider in which quotient bit selection is a function of the two most significant digits of the current partial remainder. An n-bit divider produces an n-bit quotient in redundant form in 3n gate delays using n(n-1) controlled full add/subtract circuits. Operand pre-scaling necessary for the algorithm is accomplished by a single subtraction. >

Mathematical game apparatus and method

Abstract: A method of playing a game where there is a first set of die, each of which has the numerical values of one through six thereon, and a second set of die each of which has plus, minus, division and multiplication signs thereon. The two sets of die are discharged onto a playing surface in a random pattern, and then the individual dice members of the first and second set are placed in an alternating pattern so that when the mathematical operations are performed as indicated in the alternating arrangement of the two sets of die, a desired maximum value is obtained.

Centers of generic division algebras, the rationality problem 1965–1990

Abstract: A survey is given of the rationality problem of the center of generic division algebras. Connections are given with Brauer groups of fields, geometric moduli problems and representation theory. An outline is given of recent results.

On the multiplicative structure of finite division rings

Abstract: All division ringsD of 16, 27, 32, 125 and 343 elements are shown to have aright primitive elementp such that $$\mathcal{D}* = \{ e,ep,(ep)p,...,(...(ep)p...)p\} .$$ That is, the multiplicative loop is the set of all right multiples of the identitye by the elementp. A construction of Dickson [5] is used to show that all commutative division algebras three-dimensional over a finite field not of characteristic 2 have a primitive element. Examples of division rings of 27, 29 and 211 elements with right primitive elements are given. Finally, a “pre-semifield” is exhibited that does not have a right primitive element.

Multiplication-based analog motion detection chip

Abstract: Novel use of an analog motion detection circuit is presented. The circuit, developed by Tanner and Mead, computes motion by dividing the time derivative of intensity by its spatial derivative; the four-quadrant division is realized with a multiplier within a negative feedback loop. The authors have opened the loop and characterized the circuit as a multiplication-based motion detector, in which the output is the product of the temporal and spatial derivatives of intensity, for various light levels and various moving patterns. An application to the time-to- contact computation is presented.© (1991) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Hypo cycloid reduction gear

Abstract: PURPOSE:To reduce backlash of a gear, and to eliminate play by using an interior division gear and a planet division gear, for which an inner gear and a planet gear are divided in the shaft direction respectively, and by providing an angle setting means for adjusting a relative angle of the interior division gear to the other one. CONSTITUTION:An inner gear 2, and a planet gear 5, which is rotated at an eccentric part 4 provided on an input shaft 3 of the same core as the inner gear 2, and which is revolved while it is engaged with the inner gear 2, are provided. The inner gear 2 is provided with first and second interior division gears 12, 13 divided in the shaft direction. The planet gear 5 is provided with first and second planet division gears 15, 16 engaged with the first and the second interior division gears 12 and 13, respectively. An angle setting means 9 for adjusting a relative angle of either the first or the second interior division gears 12, 13 to the other, is also provided. Backlash is thus adjusted by an easy operation even during operation, and play is reduced.

Multiple-valued current-mode arithmetic circuits based on redundant positive-digit number representations

Abstract: High-speed arithmetic algorithms and circuits based on redundant positive-digit number representations are described. To perform two-input radix-2 addition, for example, the proposed algorithm uses digit set (0, 1, 2, 3). The addition and subtraction can be performed speedily by a constant time independent of the wordlength. The n-digit multiplication and division can he performed in a time proportional to log/sub 2/ n and n, respectively. The basic arithmetic circuits are designed and implemented with multiple-valued current-mode circuits. The multiple-valued arithmetic circuits using the proposed algorithms exhibit good speed and compactness in VLSI implementation. >

Bit-serial division method and apparatus

Abstract: A bit-serial division method is disclosed for computing the value v/u, where v and u represent vectors in a canonical basis constituting elements in a finite field consisting of 2n elements. Vector u is converted from canonical basis to a dual basis, and each basis comprises n elements in the finite field ordered according to an index i that takes on values from 0 to (n-1). All bits n of the converted vector u are loaded into a shift register in parallel, then converted from dual basis back to canonical basis to produce a single bit output w₀ from a lookup table which generates bitwise the inverse of the n-bit vector u. The bits in the shift register are shifted (n-1) times to generate successive additional single bit outputs wi with said lookup table. Then each bit wi is multiplied by the vector v and a corresponding element ci in dual basis to generate a cumulative sum of these products that provides, upon completion of said number of shifts, the bit-serial division result v/u.

Vehicle speed measuring method and apparatus

Abstract: A vehicle speed measuring method and apparatus which can cope accurately with several vehicle speed sensors which produce different numbers of pulses for one rotation. Such vehicle speed sensors prepared for the method and apparatus produce predetermined different numbers of pulses for one rotation, some of such sensors defining a group wherein such numbers of pulses have a greatest common divisor greater than 1. It is first determined whether or not a particular vehicle speed sensor employed belongs to this group of sensors. When the sensor belongs to the group, pulses therefrom are frequency divided by a value obtained by division of the number of pulses produced for one rotation of the sensor by the greatest common divisor, and time data indicative of the time of appearance of a pulse by frequency division are stored into a memory for one rotation of the sensor. A period for one rotation of the sensor is calculated from such stored time data, and a vehicle speed is calculated from the period and a distance over which the vehicle runs for one rotation of the sensor.

Compile-time transformations and optimization of parallel Divide-and-Conquer algorithms

Abstract: In this paper we show how it is often possible to transform and optimize parallel algorithms based on the Divide-and-Conquer paradigm at compile time. Our goal is to make Divide-and-Conquer algorithms suitable for implementation on hypercube-like parallel architectures, such as the Connection Machine, even if the original algorithm implies a division function that is not the left-right division and/or communication pattern that cannot be implemented by direct-neighbor communication.Our tools are the formal model of the Divide-and-Conquer paradigm developed in [4] and the parallel programming language derived from this model: Divacon [2], [3].Our main results concern the replacement of last-k communication (broadcast) and mirror image communication with correspondent communication and the transformation from odd-even division to left-right division and vice versa. By using each of the techniques described in this paper it is possible to improve many Divide-and-Conquer algorithms by a factor of log(n).

Cell cycle kinetics with supramitotic control, two cell types, and unequal division: a model of transformed embryonic cells

Abstract: We develop a mathematical model of cell cycle kinetics of transformed embryonic cells. The model includes supramitotic regulation, in which decisions regarding growth control are made at a point inside the cell division cycle and their impact extends to the next decision point, located in the next division cycle. Another feature is the presence of two varieties of cells, which switch from one to the other with given transition probabilities. The third factor considered is unequal division of cells, also defined in probabilistic terms. We provide a rigorous description of the model and derivation of its equations and analyze its asymptotic properties by defining and investigating an abstract semigroup of positive linear operators in appropriate state space. The spectral properties of the semigroup yield the balanced exponential growth law for the model. To compare the model to experimental data, we derive basic pedigree statistics, β curves, and generation time correlations. We present numerical calculations based on measurements available for the embryonic cells. We conclude that to yield the experimentally obtained pedigree statistics, switches from one cell variety to the other must be quite infrequent.

A simple analog division scheme

Abstract: A technique for analog division of two voltage signals that offers high accuracy (0.5%) and relatively good response, especially when the numerator value is nearly constant, is presented. The proposed method is based on the relation of a signal's frequency to its period. The basic idea is to convert input voltage to frequency (through a voltage-controlled oscillator (VCO)) and then produce an output voltage proportional to the period of this signal. The circuit implementing this method is easy to build and may be used in many instrumentation and control applications where the reciprocal of a voltage is needed. Supporting experimental results and performance measurements are also given. >

Structure of golf score board

Abstract: A structure of a golf score board for golf cart, which is unitarily made of resilient material through shape molding process and comprises two raised side wall portions having two hook-like projecting ends, two openings, two slant faces and a division wall portion which define two receiving spaces for holding two golf balls.

Method of recording and reproducing video format signal using division video signals on a plurality of recording media

Abstract: A video format signal recording and reproducing method wherein a plurality of division video signals are obtained by dividing a single video format signal and are recorded onto a plurality of recording media, set indication ID numbers are recorded. When the division video signals are reproduced from the recording media, the set indication ID numbers are automatically discriminated. Only when the set indication ID numbers coincide each other, the reproducing operation of the single video format signal is executed.