Showing papers on "Divisor published in 1989"

High speed dividing apparatus

Abstract: An operation apparatus and method receive a dividend and a divisor as the input values of a divide operation processing, repeat a subtractive operation when the dividend and divisor are determined as being equal in sign to each other, and progress the repetition of an additive operation when the dividend and divisor are determined as being different in sign from each other. When the most significant bit of a quotient is calculated as having a negative number upon the sign equality of the dividend and divisor and when the most significant bit of the quotient is calculated as having a negative number upon the sign inequality of the dividend and divisor, an overflow is repeated at a time the other quotient bit conincides with the most significant bit of the quotient to detect it during a portion of the operation process.

Division method and apparatus including use of a Z--Z plot to select acceptable quotient bits

Abstract: An optimized division circuit and a method of implementing the circuit includes the steps of determining a Z--Z plot relationship which represents a relationship between a first divisor ratio proportional to a range of previously determined remainder values divided by the divisor and a second divisor ratio equal to a range of succeeding remainder values divided by the divisor. A completer look-up table is automatically built from the Z--Z plot relationship which includes, for each different valid combination of divisor and next remainder values, either a corresponding quotient digit or a DON'T CARE indicator. A state value, used in the logical implementation of the circuit, is then assigned to each different quotient digit. The circuit includes a divisor multiple formation circuit, a quotient determining circuit and a quotient assimilation circuit. The divisor multiple formation circuit includes a divisor multiple multiplexer. The quotient determining circuit includes a next partial remainder determining circuit and a next quotient digit selection circuit. The quotient assimilation circuit subtracts negative values of quotient digits from positive values to determine a final quotient value.

Integer division circuit provided with a overflow detector circuit

Abstract: An integer division circuit performs a division operation on a dividend and a divisor each accomplished with sign information. The circuit includes a first latch circuit for temporarily storing, as sign control data, exclusive-OR operation data of the sign information of the dividend and divisor, an operation unit for forming a division operation on absolute value data of the dividend and divisor to produce a quotient, a correction circuit for correcting a sign of the quotient in response to the sign control data, and an overflow detection circuit for performing an exclusive-OR operation on the corrected-sign of the quotient and the sign control data to produce an overflow detection signal.

Precise analyses of the right- and left-shift greatest common divisor algorithms for GF ( q )U x e

Abstract: The precise average and worst-case running times of the right- and left-shift gcd algorithms for $GF(q)[x]$ are derived. A new approximate integer model for the binary greatest common divisor algorithm is obtained. The right-shift polynomial worst case differs markedly for $q = 2$ and $q > 2$. The method also yields an easy analysis of the Euclidean algorithm.

Generalized approaches to constant division

Abstract: The division process is not only the most complex but also the most time-consuming arithmetic operation in a digital computer. There exist many types of special-purpose systems which require rapid and repeated division by a set of known constant divisors. Even in general purpose machines, since integer division takes significantly longer than additions or subtraction, if many divisions are needed, this disparity in execution time can result in a bottleneck. It is therefore beneficial to seek ways to do specific division cases faster, in order to improve the average performance of division. Numerous solutions have been proposed in response to the deficiencies of the conventional division algorithms, for applications which involve repeated divisions by known constants. The approaches in the literature are outlined and characterized with respect to timing, generality, implied redundancy, and the possibility of shared computation, parallelism,, and pipelined implementation. The application-dependent development of the constant division approaches has left a gap in the theoretical foundations of the algorithms. Here the various methods are mathematically explained and unified through the establishment of their common theoretical basis. A major intended contribution of this research is the definition of approaches to division by constants belonging to the set of integers of the form 2$\sp{n}\ \pm$ 1. Generalized algorithms for division by integers of the form 2$\sp{n}\ \pm$ 1, for an arbitrary value or values of $n$, are developed and proved correct. Implementation issues are explored in the development of design suggestions for the constant division method. The algorithms presented are a good solution to the problem of division by constants of the specific form 2$\sp{n}\ \pm$ 1, for $n$ $\in$ N, $n$ $>$ 0. The consideration of such a subset of divisor values (of the form 2$\sp{n}\ \pm$ 1) is not, however, a satisfactory solution to the general problem of constant division. Dividers designed for constant divisors in this set can trivially be extended to cover divisors of the form 2$\sp{m}(2\sp{n}\pm1)$, $m$ $\in$ N. The Euler-Fermat theorem is used to show that, with one additional multiplication, division by any integer can be converted to a division by an integer of the for 2$\sp{n}$ $-$ 1. The multiplier to be determined is established to be the value in one period of the reciprocal of the divisor. Approaches to reciprocal determination are therefore presented, specifically methods that take advantage of the special characteristics of reciprocals of integers.

Division system and its device

Abstract: PURPOSE:To realize the high-speed processing with a division device by performing the repetitive multiplication for convergence of the divisor side and the repetitive multiplication for convergence of the dividend side in parallel with each other via two multipliers. CONSTITUTION:The convergence factors obtained recurrently are repetitively multiplied by a divisor and a dividend respectively. Then the repetitive multiplication result is converged to 1 at the divisor side together with the repetitive multiplication result converted to the quotient at the dividend side respectively. In such a convergence type division, the repetitive multiplications for convergence of the divisor and dividend sides are carried out in parallel with each other via two multipliers.In other words, two multipliers 140 and 141 of m-bit Xm/2-bit are used to carry out the repetitive multiplications in parallel to each other for convergence at the denominator (divisor) and numerator (dividend) sides respectively (m: valid digit number of the data on divisor, dividend, quotient, etc.). In such a way of the parallel calculations carried out via both multipliers 140 and 141, the processing time can be shortened in a division system.

Approximated inverse number generation device for division

Abstract: PURPOSE: To efficiently generate an approximated inverse number by converting a divisor into a binary normalized form when the divisor is not a base normalized form. CONSTITUTION: The mantissa of the divisor is stored in a divisor register 2 through a divisor selector 1, ad a divisor check circuit 4 decides whether the output of the divisor register 2 is the base normalized form or not in accordance with the instruction of a base mode signal 3. In the case of the base normalized form, shift counting required for setting the output of the divisor register 2 to be the binary normalized form based on high-order five bits of the divisor register 2 is obtained in an inverse number generation data shift counting generation circuit 5. Then, only prescribed higher bits of the divisor register 2, which are required for generating the approximated inverse number based on said shift counting, is shifted left in an inverse number data shift circuit 6, and they are supplied to an approximated inverse number generation circuit 9, whereby the approximated inverse number of the divisor is generated. If the divisor is not the base normalized form, a binary normalized form shifter 8 is used and the divisor is converted into the binary normalized form so as to execute the processing. COPYRIGHT: (C)1991,JPO&Japio

Method for dividing any-length operands respectively normalized at the beginning for data processing equipment and digital divider for carrying out the method

Abstract: A fast division of two operands is achieved by using a modified "two-bit look ahead non-restoring" method For this purpose, the number of divisor multiples is selected in accordance with the number required for a maximum redundant division The multiple is unambiguously defined as a function of the divisor (DOR) and of the dividend (DIV) or part-remainder (PR) and provided by a device (SE) for the next division step following in each case For this reason, an initialisation step is also necessary in which the multiple (for example -32 D) is transferred to the first step of the division In each division step, the unshortened divisor multiple is subtracted from the dividend or part-remainder or added thereto whilst, at the same time, the same operands reduced to k (eg k = 8) bit positions are processed in a parallel-connected adder (AE1) The shortened addition result is again reduced to i (eg i = 5) bit positions and logically combined with the shortened divisor (DOR) for selecting the divisor multiple Depending on the sign (SIG) of the in each case unshortened part-remainder per division step and on the in each case associated divisor multiple, two quotient bits (QUB) are provided by a device (QE)

A parallel SRT divider for systolic linear system solvers

Abstract: The design and simulation results for a CMOS parallel SRT divider which produces a 16-bit quotient from a 16-bit floating-point dividend and a 16-bit floating-point divisor are described. The divider used mixed-radix signed-digit numbers for the quotient before decoding. A behavioral simulator which implements the detailed algorithms, has been written for the divider in C. Simulation results have been compared to computer division for 1000 random test vectors. Timing simulations using the simulator FACTS give worst-case propagation delays of 326.5 ns using 3- mu m CMOS parametric data. >

On Stöhr-Voloch's proof of Weil's theorem

Abstract: LetX be a smooth, projective curve of genusg defined over a finite field. Then there exists a finite extension fieldk=F q such that, for all sufficiently largen, (1)X imbeds in P n in such a way that the set of pointsx ofX mapped via Frobenius into the osculating hyperplane ofX atx is the support of a positive divisor and (2) the numberN of points inX(k) satisfies $$N \leqslant (n - 1)(g - 1) + (q + n)(n + g)/n.$$

On ramification divisors of functions in a punctured compact riemann surface.

Abstract: Let v be a compact Riemann surface and v' be the complement in v of a nonvoid finite subset. Let M(v') be the field of meromorphic functions in v'. In this paper we study the ramification divisors of the functions in M(v') which have exponential singularities of finite degree at the points of v-v', and one proves, for instance, that if a function in M(v') belongs to the subfield generated by the functions of this type, and has a finite ramification divisor, it also has a finite divisor. It is also proved that for a given finite divisor d in v', the ramification divisors (with a fixed degree) of the functions of the said type whose divisor id d, define a proper analytic subset of a certain symmetric power of v'.

System for optimizing common divisor

Abstract: PURPOSE:To shorten the execution time of a program by using fast multiplication when divisors are equal even when dividends are different. CONSTITUTION:A divisor definition inspecting means 24 inspects whether or not the value of the divisor between a text being checked at present and a common divisor text is chanted. A text deformation means 25 deforms the present text and the common divisor text to a text to find the inverse of the divisor and the multiplication text of a found inverse and the dividend in case where no divisor is changed by the divisor definition inspecting means 24. And an object program can be generated by using the multiplication realizable an operation at speed higher than division. In such a way, it is possible to shorten the execution time of the program.

The average prime divisor of an integer in short intervals

Abstract: and as usual co(n) is the number of distinct prime factors of n, f2(n) is the total number of prime factors of n, f II n means that p~ (p prime) exactly divides n. It was shown in [1] that, for each fixed natural number m, there exist computable constants el, e z, ..., era, fa,f2 ..... fro, 0 2). These questions were considered in a general setting by De Koninck and Mercier [2], where under suitable conditions asymptotic relations of the form (1.3) Y~ f(P(n)) = (1 + o(1)) Z f(n) (x ~co)

Square root arithmetic processing system

Abstract: PURPOSE:To obtain the square root of one digit in one operation cycle by performing the square root arithmetic operation of operation equation Rn= Rn-1-(4*An-1+1) from an operand with a base 2 by a square root extraction method by using a high base/non-recovery type division device by a separation method. CONSTITUTION:Equation II can be obtained by rewriting subtraction is square root operation equation I to addition using a complement. In case of finding inversion (4*An-1) in equation II, it is taken from a divisor register before updating not from a divisor register DSR1 in which a value to be set on a subtraction register SR3 is updated. In other words, a value in which the complement to 1 of the value multiplied by four (8 times) of the value in which the value of a divisor register DSR in a preceding cycle is left-shifted by one bit (2 times) is taken, and the value in which the complement to 1 of the value multiplied by eight of the carry signal CARRY of partial solution obtained in the arithmetic cycle, that is, the value left-shifted by three bits is taken are set on the subtraction register SR3. Therefore, it is possible to execute the arithmetic operation of equation I in one operation cycle by providing the subtraction register SR and using the division device by the separation method.

Floating-point divider

Abstract: PURPOSE:To obtain an approximate inverse number without increasing an LSI even when table information are beyond memory capacity by providing a circuit for preparing higher 2 bits of approximate inverse and a table for lower 18 bits of approximate inverse (memory). CONSTITUTION:When the execution of a floating-point dividing instruction is started, a divisor to be set to a divisor register 2 is supplied through a digit normalizing circuit 4 to a divider 10 and supplied to a bit normalizing circuit 5. Then, a memory referring address is prepared to obtain the approximate inverse number. A table for lower 18 bits of approximate inverse 8 is referred according to addresses d2, d3...d11 and approximate inverses S3, S4...S20 are obtained. Then, according to the correspondence between the address and higher 2 bits of an inverse an S1 and an S2 are prepared in a circuit for preparing higher 2 bits of approximate inverse 7. Thus, approximate inverse numbers 1, S1, S2...S20 can be obtained. Then, since the approximate inverse can be obtained without increasing the number of the LSIs even when the table information to accompany the divisor are over the memory capacity, hardware quantity can be reduced.

Extension accuracy dividing processing system

Abstract: PURPOSE:To effectively execute the extension accuracy dividing instruction at high speed by extending a divisor register and a partial residual register with the data width of a dividing circuit. CONSTITUTION:In a dividing circuit composed of a divisor register 1', a multiple generating circuit 2 of the divisor, an adder 3, a partial quotient predicting device 4, a partial quotient generating part 5 and a partial residual register 6', only the divisor register 1' and the partial residual register 6' are extended by the data width of the dividing circuit, the divisor register 1' is extended to a high-order side 1a' and a low-order side 1b' and the partial residual register 6' is also extended to a high-order side 6a' and to a low-order side 6b'. Other arithmetic circuit is used by a time division appropriately. Thus, without expanding the data width of a high base non-recovering type dividing circuit, an extension accuracy dividing instruction can be executed effectively at high speed.