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Showing papers on "DVB-S2 published in 2013"


Proceedings ArticleDOI
02 Dec 2013
TL;DR: An original solution that combines repetition of the concerned layers and the write disable of the a posteriori information memory is proposed that led to an average air throughput of 200 Mbit/s with a parallelism of 45 and a clock frequency of 300 MHz on CMOS technology.
Abstract: Layered decoding is known to provide efficient and high-throughput implementation of LDPC decoders. However, the implementation of layered architecture is not always straightforward because of memory update conflicts in the a posteriori information memory. In this paper, we focus our attention on a particular type of conflict that is due to multiple-diagonal sub-matrices in the DVB-S2, -T2 and -C2 parity-check matrices. We propose an original solution that combines repetition of the concerned layers and the write disable of the a posteriori information memory. The implementation of this solution on an FPGA-based LDPC decoder led to an average air throughput of 200 Mbit/s with a parallelism of 45 and a clock frequency of 300 MHz. Increasing the parallelism to 120 led to an average air throughput of 720 Mbit/s with a clock frequency of 400 MHz on CMOS technology.

9 citations


Proceedings Article
11 Nov 2013
TL;DR: Simulation results, obtained by using two test images with different texture, showed that QPSK modulation is more robust compared to 8 PSK modulation in the same propagation conditions.
Abstract: This paper presents simulation model of the DVB-S2 (Digital Video Broadcasting - Satellite - Second Generation) system implemented in Simulink, Matlab. The model provides simulation of the DVB-S2 system parameters in AWGN (Additive White Gaussian Noise) channel. The aim of this model is to propose optimal DVB-S2 parameters in different propagation conditions. The simulation offers two modulation scheme options QPSK (Quadrature Phase Shift Keying) and 8PSK (8 Phase Shift Keying) with different code ratio values. During the simulation, BER (bit error rate) and PER (packet error rate) are calculated and the constellation diagram is observed. Simulation results, obtained by using two test images with different texture, showed that QPSK modulation is more robust compared to 8PSK modulation in the same propagation conditions. Simulink model results were compared with measurements of several Astra 1 satellite (19,2° E) transponders parameters. Lab-measured values achieved higher SNR values than simulation cases because of real wireless channel conditions. Optimal operation parameters for a DVB-S2 system according to channel conditions and the required bit rate are proposed.

9 citations


Proceedings ArticleDOI
09 Jun 2013
TL;DR: The purpose of this paper is to investigate utility function based algorithms, and it is shown that the algorithm implemented is an important issue.
Abstract: Satellite Digital Video Broadcasting is deeply changing : the next generation is dedicated to packet based communications and introduces (like many modern physical layers : WiMax, hsdpa, ...) fade mitigation techniques leading to variable throughput. Such tremendous changes need to be taken into account and the scheduling entity needs to be revisited. The purpose of this paper is to investigate utility function based algorithms. Such techniques have already been studied but never within this context. Dvb-s2 frames can encapsulate numerous ip packets, can offer variable payload length as well as variable transmission time, because of acm techniques. A more general approach is needed to encompass theses properties. As a consequence, the number of solutions among which a scheduler has to find the better is increased. We will then show that the algorithm implemented is an important issue.

7 citations


Patent
04 Sep 2013
TL;DR: In this article, a digital video broadcasting-satellite-second generation (DVB-S2) based transmission and reception apparatus and method operable in circumstances of a low signal to noise ratio (SNR) is presented.
Abstract: Provided is a digital video broadcasting-satellite-second generation (DVB-S2) based transmission and reception apparatus and method operable in circumstances of a low signal to noise ratio (SNR), the DVB-S2 based transmission and reception apparatus including a DVB-S2 based transmitter, a mapping unit to determine bit mapping based on at least one of a state of a transmission channel and an area to be applied, and a physical layer frame (PLframe) replica processing unit to repeat a PLframe in which a physical layer header (PLheader) corresponding to a spreading factor (SF) is inserted.

6 citations




Proceedings ArticleDOI
14 Oct 2013
TL;DR: A variation of simulated annealing algorithm for optimizing two-dimensional constellations with up to 32 signals is used, focusing on optimizing the average mutual information, which is shown to be the relevant measure for pragmatic schemes usually adopted in the receiver.
Abstract: In this paper we use a variation of simulated annealing algorithm for optimizing two-dimensional constellations with up to 32 signals. We focus on optimizing the \emph{pragmatic} average mutual information, which is shown to be the relevant measure for pragmatic schemes usually adopted in the receiver. The method allows the joint optimization of constellation and binary labeling. We investigate the performance of the optimized constellation over both AWGN channel and nonlinear satellite channel. The optimized constellations perform considerably better than the conventional Amplitude Phase Shift Keying (APSK) modulations over the AWGN, used in the current digital video broadcasting standard (DVB-S2). As for the nonlinear channel, we consider the so called Soft Limiter model for the high power amplifier. We provide simulation results in realistic scenarios using the DVB-S2 standard LDPC to show the gains obtained by the proposed constellations.

2 citations


Proceedings ArticleDOI
14 Oct 2013
TL;DR: It is shown that achievable rate calculations are highly-predictive of actual performance and of proper IBO, and modification to the constellation ring ratio can provide significant savings in SNR, at least for the adopted nonlinear Saleh model.
Abstract: Single-user coded 16-APSK transmission is studied from the perspective of achievable information rate and channel simulation, in the context of DVB-S2 over a nonlinear satellite channel. Achievable information rates are calculated as a function of downlink SNR and input backoff for the nonlinear amplifier, for both a memoryless end-to-end model and for a model with memory-order two. These provide benchmarks for real decoder simulations, and it is shown that achievable rate calculations are highly-predictive of actual performance and of proper IBO. We also show modification to the constellation ring ratio can provide significant savings in SNR, at least for the adopted nonlinear Saleh model. Finally, a two-pass decoding that employs hard-decision feedback from the LDPC decoder is able to gain another 0.4 dB in performance without significant complexity increase. This gain is predicted by our achievable rate analysis.

2 citations


Journal Article
TL;DR: The design and implementation of SRRC filter as part of the Baseband shaping and Quadrature modulation module of DVB-S2 standard for the three rolloff factors 0.20, 0.25, and 0.35 is focused on.
Abstract: The new bandwidth-efficient DVB-S2 (EN302307) standard, the successor of DVB-S and DVB-DSNG is designed to address the challenges of cost-effectively transmitting high-quality video and advanced services via satellite. This paper focuses on the design and implementation of SRRC filter as part of the Baseband shaping and Quadrature modulation module of DVB-S2 standard for the three rolloff factors 0.20, 0.25, and 0.35. It is a pulse shaping filter which aims at minimising ISI.Direct form symmetric structure of FIR filter is used to design SRRC filter of order 96using MATLAB and FPGA implemented using ALTERA Quartus II.This paper will deliver the results of SRRC filter for different roll-offs along with the performance gain comparisons of DVB-S and DVB-S2 roll-offs.

1 citations


Proceedings ArticleDOI
02 Jul 2013
TL;DR: A new decoder architecture is proposed which employs HSS algorithm and simple check node update algorithm and 7 times of decoder throughput may be improved compared to conventional one.
Abstract: This paper proposed a new decoder architecture which employs HSS algorithm and simple check node update algorithm. Memory architecture is a major point of in terms of high speed and area of implementation, therefore the efficient memory design to accelerate decoding throughput is studied. In conventional decoder architectures, p- parallelism, dc-serialism, and q-serialism are required. This paper attempted memory division to obtain dc-parallelism and memory sharing to reduce area, 7 times of decoder throughput may be improved compared to conventional one.

1 citations



Journal Article
TL;DR: Experimental result shows the DVB-S2 GS extraction and analysis method can restore IP data in application layer rapidly and accurately, and can realize the processing of GS.
Abstract: Along with the combination of satellite and Internet technology, business lines transmitted by satellite Digital Video Broadcasting-Satellite(DVB-S) channel increases rapidly. The first generation system can not meet the need of the fast increasing IP business, hence, an entirely new Generic Stream(GS) is introduced in DVB-S2 standard. Aiming at the problem that the existing satellite terminal equipment can not process GS very well, this paper presents a DVB-S2 GS extraction and analysis method according to the form of generic stream, the arrangement method of GS in base-band frame and feature of Generic Stream Encapsulation(GSE). It analyses the encapsulation mode of base-band frame and GSE of GS, and tests some actual data. Experimental result shows the method can restore IP data in application layer rapidly and accurately, and can realize the processing of GS.

Proceedings ArticleDOI
01 Jul 2013
TL;DR: An energy-driven scheduling algorithm with optimized throughput, termed as Energy Efficiency Fair (EEF) queuing algorithm, is proposed, which improves a scheduling mechanism of a two-step scheduler by selecting frames to be transmitted next according to “energy efficiency” policy developed.
Abstract: The continuous growth in wireless data traffic results in the increase in total energy consumption of wireless networks. Therefore, energy-efficient solutions are extremely required to minimize the energy consumption over the entire network. In this paper, an energy-driven scheduling algorithm with optimized throughput, termed as Energy Efficiency Fair (EEF) queuing algorithm, is proposed. Based on energy efficiency of each modulation and coding scheme (MODCOD) available in Digital Video Broadcasting - Satellite Second Generation (DVB-S2), the EEF algorithm improves a scheduling mechanism of a two-step scheduler by selecting frames to be transmitted next according to “energy efficiency” policy developed. The EEF is compared with Round Robin (RR) algorithm, and a gain in energy efficiency of 47% is obtained when different modulation schemes with common code rate are implemented. Furthermore, EEF outperforms RR by 264% concerning the useful transmitted bits when QPSK modulation scheme with different coding rates is used.


Proceedings ArticleDOI
14 Oct 2013
TL;DR: Two-way amplify-and-forward relaying between earth terminals with both users sharing the same bandwidth offers an improvement in spectral efficiency of 100%, relative to traditional frequency-multiplexing, without increase in downlink resources.
Abstract: Two-way amplify-and-forward relaying between earth terminals with both users sharing the same bandwidth offers an improvement in spectral efficiency of 100%, relative to traditional frequency-multiplexing, without increase in downlink resources. This co-existence is possible due to the side-information retained in each receiver about its own ‘echo’ signal. While this has been widely studied in the context of linear relaying, two-way amplify/forward on a nonlinear satellite channel raises additional questions, dealing with synchronization to allow mitigation of self-interference; the achievable information rates and optimal amplifier backoff; and the performance of a ‘real’ two-way system in the context of DVB-S2 coding and modulation.

Journal ArticleDOI
TL;DR: The proposed LDPC encoding architecture is based on a parallel 360 bits-wise operations, and the key issues for realizing high speed are using the two kinds of index addresses and make use of memories efficiently.
Abstract: In this paper, we proposed high speed LDPC encoder architecture for DVB-S2 standard. In conventional algorithm, the processes of parity calculations are serial fashion. Therefore conventional algorithm need clocks of number of parity. The proposed LDPC encoding architecture is based on a parallel 360 bits-wise operations. The key issues for realizing high speed are using the two kinds of index addresses and make use of memories efficiently. We implemented a half rate LDPC encoder on an FPGA, and confirmed its maximum throughput is up to 10 Gbps on 100MHz clock.

Book ChapterDOI
Min-Goo Kang1, Y. J. Woo1, Kilhung Lee, I. K. Kim, Jong Sik Lee 
01 Jan 2013
TL;DR: This software-based receiver and analyzer system of Digital Video Broadcasting_2nd Generation Terrestrial (DVB-T2) were implemented by memory sharing techniques for minimization of system overloads.
Abstract: In this paper, a receiver and an analyzer system of Digital Video Broadcasting_2nd Generation Terrestrial (DVB-T2) were designed using Digital Video Broadcasting_2nd Generation Satellite (DVB-S2), and Digital Video Broadcasting_2nd Generation Cable (DVB-C2). This software-based receiver and analyzer system were implemented by memory sharing techniques for minimization of system overloads.

Journal ArticleDOI
TL;DR: In order to solve the problem of high consumption of resources, the design of decoder adopted serial architecture, the decoding delay was greatly reduced by clever design of interleaver structure, and the decoding throughput reaches 125Mbps.
Abstract: Full parallel architecture for DVB-S2 LDPC was implemented on the platform of FPGA, in this process, the pipeline technology was introduced, and the method of FIFO and multiple RAM group used at the same time was also used, the problem of storing the parity check matrix was effectively overcomed, and the coding rate reaches 125Mbps. In order to solve the problem of high consumption of resources, the design of decoder adopted serial architecture, the decoding delay was greatly reduced by clever design of interleaver structure, and the decoding throughput reaches 125Mbps, moreover utilization of registers and logic elements is less than 1%.