Showing papers on "Effective number of bits published in 1986"

High efficiency technique for coding a digital video signal

Abstract: The invention relates to a high efficiency apparatus for coding digital video data in which the number of bits per picture element in the video data such as a digital video signal or the like is compressed. The video data of a television picture plane is divided into a number of three-dimensional blocks, i.e., spatial blocks. The picture element data in the block can be coded by the reduced number of bits by the bit compression by performing the coding process adapted to the narrowed dynamic range on the basis of the correlation among the picture elements in each block. The transmission data of the number of bits reduced as compared with the number of bits of the original data can be formed. By coding only the necessary frame by discriminating the movement of the image in the block, the redundancy in the direction of time can be removed.

Serial-to-parallel and parallel-to-serial converter

Abstract: A serial-to-parallel and parallel-to-serial data format converter has a plurality of first-in, first-out (FIFO) buffer memory devices, an input circuit for receiving serial data bits, an output circuit for outputting serial data bits and a clocking circuit for clocking selected ones of the data bits into and out of selected ones of the FIFO buffer memory devices. The clocking circuit clocks serial data bits either into or out of each of the FIFO buffer memory devices at a rate slower than the rate of the receipt of the serial data bits by the input circuit, or the rate of the outputting of serial data bits by the output circuit, respectively.

ECC circuit failure detector/quick word verifier

Abstract: A circuit for quickly determining if all of the data bits in an ECC word are correct and/or for detecting failures in an error detection syndrome generation path in an ECC circuit, where the ECC circuit utilizes an error correction code with two diagonal quadrants in the code matrix composed entirely of columns which have an even number of ones, and with the other two quadrants composed entirely of columns which have an odd number of ones. In one embodiment, the circuit comprises means for generating a parity bit, Pk, for each of K data fields in the ECC word; means for comparing logical combinations of these parity bits to logical combinations of the memory check bits, Cj, to form H bits; and means for logically combining these H bits to form a D bit. This D bit may be compared to the binary (non-carry) sum of the syndrome bits to detect syndrome generation path failures. This D bit may also be used to determine if the data bits in an ECC word are correct, a number of cycles before the completion of the normal ECC operation.

Duplicate digital date recording apparatus for enhancing bit error rate performance of a data storage medium

Abstract: Apparatus for enhancing the bit error rate performance of a storage medium, such as magnetic tape, magnetic disk, optical disk, or an equivalent thereof, includes two data transmission channels for recording in duplicate a stream of data bits corresponding to an information-bearing signal, each recorded bit stream being potentially influenced by a pattern of statistically distributed recording surface defects. During playback, error detection and correction circuitry for each channel provides an alarm signal synchronized with each uncorrected error condition in the corresponding stream of playback bits. A control circuit, responsive to the alarm signals from each channel, serves to interleave error-free bits from one channel, to the exclusion of error bits from the other channel, to provide a single continuous stream of relatively error-free bits corresponding to the information-bearing signal recorded.

Digital filter circuit

Abstract: A digital filter circuit includes first and second counters which set and reset a latch circuit at predetermined counts. Clock pulses and the input signal are passed through a gate circuit to the first counter which outputs a set signal to the latch circuit only if the input signal is maintained at a high level for the predetermined count. Clock pulses and the inverted input signal are passed through a gate circuit to the second counter which outputs a reset signal to the latch circuit only if the input signal is maintained at a low level for the predetermined count. In this manner noise pulses on the input signal are filtered out of the output signal obtained from the latch circuit.

Gate array circuit for decoding circuits

Abstract: A decoder circuit for decoding different combinations of supplied original input address bits, comprising at least one predecode circuit responsive to the original input address bits for producing predecoded signal bits from the input address bits, and a plurality of decoder units including at least one decoder unit responsive to at least two different combinations of the original input address bits, wherein the decoder units comprises a decoder unit responsive to selected ones of the predecoded signal bits alone and a decoder unit responsive to at least one of the predecoded signal bits and at least one of the original input address bits.

Method and apparatus for digitizing television signals

Abstract: An arrangement for digitizing television signals, particularly the staircase portion of the vertical interval test signal transmitted by the British Broadcasting Corporation and the Independent Broadcasting Authority comprises a luminance/chrominance separator (2) and two analog to digital converters (ADC's) (6, 9). The ADC(6) digitizes the color subcarrier which has a low amplitude but a high frequency while the ADC(9) digitizes the high amplitude low frequency luminance portion. The digitized samples are stored in two sections of RAM (11, 13) under the control of a write address generator (25) and two respective write control circuits (14,17). The ADC(6) operates at 4 fsc and has a resolution of 7 bits while the ADC(9) operates at one sixteenth of that rate and has a resolution of 10 bits. This enables a full 10 bit resolution to be obtained without requiring a high cost ADC.

Cyclic digital information transmission system

Abstract: According to a method of this invention, information and check bits in one frame of information to be transmitted are divided into two fields (i.e., a first field not requiring addition of fixed bits, and a second field requiring addition of fixed bits). The characteristic inherent to the bit pattern formed of a sync signal and the second field does not appear in the first field so that the sync signal can be discriminated. The number of fixed bits inserted in one frame can thus be decreased, and transmission efficiency can be improved.

Digital signal analyzer with analog display

Abstract: A digital signal having N bits is converted to a signal having Y of the N bits, according to their order of significance in the N-bit signal. Y is less than N. The Y-bit signal is converted to an analog voltage. The analog voltage provides an indication of information represented by the selected Y bits in the N-bit signal.

Digitising television signals

Abstract: An arrangement for digitising television signals, particularly the staircase portion of the vertical interval test signal transmitted by the BBC and the IBA, comprises a luminance/chrominance separator (2) and two analogue to digital converters (ADC's) (6,9). The ADC(6) digitises the colour subcarrier which has a low amplitude but a high frequency while the ADC-(9) digitises the high amplitude low frequency luminance portion. The digitised samples are stored in two sections of RAM (11, 13) under the control of a write address generator (25) and two respective write control circuits (14,17). The ADC(6) operates at 4, sc and has a resolution of 7 bits while the ADC(9) operates at one sixteenth of that rate and has a resolution of 10 bits. This enables a full 10 bit resolution to be obtained without requiring a high cost ADC.

Digital-to-analog converter and method relating thereto

Abstract: Digital signals are processed by a first accumulator (26) to generate most significant bits which represent the signal to be converted but with truncation noise. The error signals from the first accumulator are processed by a second; sccumulator (36) to generate a second set of most significant bits which are used to remove the truncation noise. The most significant bits from the second accumulator are converted to analog form, differentiated and then combined with the most significant bits from the first accumulator after being converted from digital to analog form. The combined signal Is then amplified and filtered.

Ic chip error detecting and correcting with automatic self-checkingand method therefor.

Abstract: Error detecting and correction operations for a plurality of input bits comprised of input data bits (ID0-ID39) and associated check bits (CB0-CB7) are implemented using two IC chips in order to overcome chip output limitations. In addition, redundancies derived from the use of two IC chips are employed to provide automatic self-checking of the detecting operation of each chip. The use of two identical IC chips (10 and 10') for this purpose is made possible by employing a specifically chosen inversely symmetrical Hamming code and by wiring the input data bits and the input check bits in an inverse manner with respect to the input terminals of the two IC chips. As a result, even though each IC chip performs the same error detecting and correcting operations, it does so inversely with respect to the input data bits and the input check bits so that each IC chip is able to provide one-half of the required output bits.

Ic chip error detecting and correcting with automatic self-checking

Abstract: Error detecting and correction operations for a plurality of input bits comprised of input data bits (ID0-ID39) and associated check bits (CB0-CB7) are implemented using two IC chips in order to overcome chip output limitations. In addition, redundancies derived from the use of two IC chips are employed to provide automatic self-checking of the detecting operation of each chip. The use of two identical IC chips (10 and 10') for this purpose is made possible by employing a specifically chosen inversely symmetrical Hamming code and by wiring the input data bits and the input check bits in an inverse manner with respect to the input terminals of the two IC chips. As a result, even though each IC chip performs the same error detecting and correcting operations, it does so inversely with respect to the input data bits and the input check bits so that each IC chip is able to provide one-half of the required output bits.

Quasi-analog reconstruction of an amplitude and frequency varying analog input signal

Abstract: A quasi-analog reconstruction of an amplitude and fre­ quency varying analog input signal is produced as a staircase waveform, each step voltage of which is generated by utiliz­ ing the binary bits of a corresponding codeword of a PCM signal derived from the analog input signal. In order to achieve optimum resolution, the binary bits of each PCM codeword are considered as C in number, of which an A number are major bits and a B number are minor bits; the A bits being converted to a (2 A -1) number of discrete decimal bits, each of which controls the switching to and from a series voltage summation line (20) of a discrete vol­ tage V c where V max is substantially the peak voltage amplitude to be provided in the reconstructed signal. Individual ones of the B bits directly control the individual switching to and from the summation line of discrete voltages of unequal magnitudes declining in one-half voltage increments from Vc / 2 to .