Showing papers on "Equal-cost multi-path routing published in 1982"

A Responsive Distributed Routing Algorithm for Computer Networks

Abstract: A new distributed algorithm is presented for dynamically determining weighted shortest paths used for message routing in computer networks The major features of the algorithm are that the paths defined do not form transient loops when weights change and the number of steps required to find new shortest paths when network links fail is less than for previous algorithms Specifically, the worst case recovery time is proportional to the largest number of hops h in any of the weighted shortest paths For previous loop-free distributed algorithms this recovery time is proportional to h2

A Distributed Routing Design for a Broadcast Environment

Abstract: In this paper, we will present the need for distributed network control in a packet radio environment, the criteria used for its evaluation, and an overview of the network algorithms chosen to maintain routing information and to route user traffic The routing algorithm, known as tiered rings, functions by building a distributed tree of shortest path routes to each packet radio in the network The information kept by each node grows only linearly as the network expands The design uses the radio channel efficiently by providing shortest path routing and by taking advantage of the information available in a broadcast environment

On decentralized dynamic routing for congested traffic networks

Abstract: The problem of routing traffic through single destination congested networks is considered, when the network has deterministic inputs and may contain looping paths. A decentralized dynamic routing strategy is proposed which assures that no traffic is directed around loops.

On Routing for Custom Integrated Circuits

Abstract: This paper presents a novel and effective strategy for routing custom integrated circuits as well as solutions to subproblems associated with this strategy. Given an initial placement of rectangular blocks, the routing strategy includes the following major steps: construction of a channel graph, estimation of channel widths (based on a statistical model for signal nets and topological routing of power and ground nets), placement modification to include the estimated channel widths, topological routing for signal nets, and finally track assignment. Besides presenting an overview of our strategy, the following topics will be discussed in some detail: (1) necessary and sufficient conditions and a simple algorithm for single layer topological routing of power and ground nets, (2) a quadratic programming formulation for the placement modification problem, and (3) a fast algorithm for obtaining topological routes for signal nets.

Hardware Support for Automatic Routing

Abstract: A system for automatic routing based on an iterative application of Lee's algorithm is presented. An extended cell admissibility is defined for continuous design rules in coarse rectangular grids. Combined hardware and software design strategies are applied towards the definition of data structures and their kernel primitives for automatic routing. The hardware architecture and the implementation of specific structures are discussed. The resulting extended routing unit is used in a CAD system. Thus the throughput of the iterative router is improved by a factor of 5 compared to the equivalent software process. Finally the architecture of a high speed stand-alone routing processor is presented.

A Minimum-Impact Routing Algorithm

Abstract: A routing heuristic is presented that routes two-terminal nets one at a time, for each net choosing the path so as to avoid adversely impacting the nets not yet routed. An algorithm is presented and proved to correctly implement this heuristic; the computational complexity of that algorithm is shown to be polynomially bounded, but perhaps still too great to be of practical use. Another, speedier algorithm is presented that seems to approximate the heuristic rather closely. Strong evidence is given that the Lee routing algorithm is in some sense inadequate to implement this heuristic. The heuristic has been applied, with very encouraging results, to a specific routing problem: the routing of a channel in which all four sides of the channel may contain terminals. This problem arises in the layout of custom VLSI.

An Analytical Method for Compacting Routing Area in Integrated Circuits

Abstract: An analytical method is proposed for solving a routing area compaction problem in building block integrated circuits. Related minimization is performed with a linear programming technique. Minimum channel dimensions are calculated for a preliminary routing; these dimensions are used to construct routing constraints. Placement constraints are added for the interrelations between placement and routing. This combined set of constraints leads to a least overestimation of routing area and under certain conditions guarantees routing feasibility. Computational complexity and existence of a solution are discussed.

The 1-2-3 routing algorithm or the single channel 2-step router on 3 interconnection layers

Abstract: In this paper an algorithm is presented for the single channel routing on 3 interconnection layers. First some general characteristics of routing on 3 interconnection layers are presented. Then the specifications are introduced of the routing problem on 3 interconnection layers that will be considered. Pins will be allowed to come out on both the diffusion/poly layer and the second metal layer with the routing done on both the first and second metal layer. If only the first metal layer was to be used horizontally then the routing problem could be solved by a simple left-edge channel algorithm. However the 1-2-3 algorithm presented here will solve identical problems with a smaller number of tracks and via's since it makes use of some specific characteristics of routing on 3 interconnection layers.

Two-Dimensional Channel Routing and Channel Intersection Problems

Abstract: A two-dimensional channel routing program for hierarchical IC layout with orthogonal building blocks of variable size and shape is presented. A two dimensional channel model and a one layer channel router are used. A detailed description of the routing scheme which avoids the generation of "switch box" problems is given. The behavior of the two-dimensional routing algorithm to single and coupled channel intersections is demonstrated.

Routing of telephone traffic to minimize network blocking

Abstract: The problem of optimum routing of telephone traffic to minimize network blocking is formulated for a class of routing schemes. The necessary conditions for minimum-blocking routing are shown to be analogous to conditions for minimum-delay routing in a store-and-forward data network. A method is described for calculating an optimum routing on the basis of centralized computational for the network. Owing to its computational complexity, however, the method is more useful for off-line studies than for real-time adaptive routing.

A routing scheme for integrated networks

Abstract: A routing scheme using delay, bandwidth and reliability measures is presented, and flow control is partially included in the method. Decisions are distributed, and the routing tables at each node contain lists of non-dominated best paths to all other nodes. Two algorithms are presented for constructing the tables, and simulation results show that their overheads are comparable to those of existing algorithms. The routing scheme is suitable for integrated packet switched and circuit switched computer networks.