Showing papers on "Fast packet switching published in 1981"

A Survey of Interconnection Networks

Abstract: Concurrent processing depends on interconnection networks for communication among processors and memory modules. Various network topologies and switching strategies are covered here.

Effects of Packet Losses in Waveform Coded Speech and Improvements Due to an Odd-Even Sample-Interpolation Procedure

Abstract: We have studied the effects of random packet losses in digital speech systems based on 12-bit PCM and 4-bit adaptive DPCM coding. The effects are a function of packet length B and probability of packet loss P L . We have also studied tbe benefits of an odd-even sample-interpolation procedure that mitigates these effects (at the cost of increased decoding delay). The procedure is based on arranging a 2B -block of codewords into two B -sample packets, an odd-sample packet and an even-sample packet. If one of these packets is lost, the odd (or even) samples of the 2B -block are estimated from the even (or odd) samples by means of adaptive interpolation. Perceptual considerations indicate that packet lengths most robust to losses are in the range 16-32 ms, irrespective of whether interpolation is used or not. With these packet lengths, tolerable P L values, which are strictly input-speech-dependent, can be as high as 2 to 5 percent without interpolation and 5 to 10 percent with interpolation. These observations are based on a computer simulation with three sentence-length speech inputs, and on informal listening tests.

Packet Switching Interconnection Networks for Modular Systems

Abstract: Adding buffers to a packet switching network can increase throughput in certain system architectures. A word of warning—don't make them too large.

Interconnection Networks Using Shuffles

Abstract: Networking techniques allow several processors within a multiprocessing system to cooperate efficiently on a single large problem.

Deadlock-Free Packet Switching Networks

Abstract: Deadlock states have been observed in existing computer networks, emphasizing the need for carefully designed flow control procedures (controllers) to avoid deadlocks. Such a deadlock-free controller is readily found if we allow it global information about the overall network state. Generally, this assumption is not realistic, and we must resort to deadlock-free local controllers using only packet and node information. We present here several types of such controllers, we study their relationship and give a proof of their optimality with respect to deadlock-free controllers using the same set of local parameters.

Some Complexity Results in the Design of Deadlock-Free Packet Switching Networks

Abstract: Deadlocks are very serious system failures and have been observed in existing packet switching networks (PSN’s). Several problems related to the design of deadlock-free PSN’s are investigated here. Polynomial-time algorithms are given for some of these problems, but most of them are shown to be NP-complete or NP-hard, and therefore polynomial-time algorithms are not likely to be found.

Routing, Flow, and Congestion Control in the Datapac Network

Abstract: Datapac is the TransCanada Telephone System's public packet-switched network, based on the Northern Telecom SL-10 Packet Switching System. The primary packet-switched communications facility offered by the SL-10 in Datapac is a virtual circuit service for which several types of customer interfaces are available. The virtual circuit service relies on a datagram facility for basic internodal communications. This paper characterizes the virtual circuit and datagram communications layer of Datapac and presents the routing, flow, and congestion control techniques currently in place for these two layers. Also, the additional measures used to control international virtual circuits are discussed.

Performance Evaluation of a Variable Frame Multiplexer for Integrated Switched Networks

Abstract: A scheme which multiplexes long messages and single packets using a time-varying frame is presented. Long messages, generated from a fixed number of terminals, immediately access a main trunk, sharing a dynamically dedicated subchannel in a roundrobin fashion. Fixed size packets arrive with Poisson statistics in a FIFO queue and are served through the same trunk, using the remaining capacity. The two traffic categories share an integrated variable length frame. The frame length is determined by the volume of the increasing traffic at the beginning of the frame and cannot exceed a maximum value. Analysis of the performance of the system is carried out using finite population round-robin processor sharing and M/G/N queueing techniques. Simplifying modeling assumptions are checked with simulation. A comparison with fixed frame schemes demonstrates the superiority of the variable frame, in terms of more efficient bandwidth utilization.

Analysis of Packet Network Congestion Control Using Sparse Matrix Algorithms

Abstract: The purpose of this study is twofold. First the study illustrates the utility of applying sparse matrix methods to packet network models. Secondly, these methods are used to give new results about the control of store and forward congestion in packet networks. Store and forward congestion (node to node blocking) reduces the effective traffic carrying capacity of the network by unnecessarily idling network resources. This study shows how store and forward congestion can be controlled by a combination of buffer reservation and processor capacity allocation. The scheme presented is analyzed using a Markovian state-space model of two coupled packet switches. The model contains more detail than previous analytic models. It is therefore solved using numerical sparse matrix methods. The results show that the combination of buffer reservation and processor capacity allocation gives strictly nondecreasing network output as a function of increasing network input load, i.e., undesirable store and forward congestion effects are eliminated.

Combined circuit and packet switched system

Abstract: A new type of exchange system is disclosed which is suitable for the use in a facsimile communication system in which a large amount of information is transmitted in one direction, and the opposite direction has a small amount of information to be transmitted. According to the present invention, said large amount of information is transmitted using a circuit switching technique which assigns a fixed circuit to the forward direction to transmit said information, and a control signal or an acknowledgement signal in the backward direction from the receiving terminal, is handled through a packet switching technique in which a plurality of calls share a single transmission line or a time slot. Thus, a transmission line is used with the same efficiency as packet switching although information is transmitted mainly in one direction, and the switching load of the exchange is as small as in circuit switching.

Process and apparatus for digital data communication using packet switching

Abstract: The consequences of the loss of a packet are attenuated in a digital data communication apparatus using packet switching by structuring the digital data as multibit words into frames having a fixed length l and assembling the frames into packets all having the same predetermined length L=kl, where k is a predetermined integer. Continuity index words incremented by one each time a new frame or packet is assembled may be located into the frame locking word or the packet prefix. Then the number of packets which are lost may be determined at the receiver location by monitoring the successively received index words. When the digital data represent successive samples which are correlated, for instance when such samples represent a sound, substitution data may be generated at the receiver location and used in place of the missing data.

Packet-based telecommunication network

Abstract: Multiservice packet telecommunication network. It comprises a plurality of subscriber's stations each having a plurality of digital data sources and digital data receivers and data switching networks connected to said stations and therebetween through incoming and outgoing data links. The data are formed in packets having an information field, an address field and a start word and end word field. The address field is fulfilled by a plurality of operations to be controlled in the packet switching networks along the packet route. Each address is cleared when the switching operation which it defines is achieved. The switching operations are made in real time due to the lay out of equipments inserted in the incoming channels to the switching networks.

Packet synthesizing system

Abstract: PURPOSE:To improve the efficiency of synthesis of packets, by sending stored packets out of a packet storage memory to a circuit when coupling with a next packet is not indicated at a packet transmitter and receiver. CONSTITUTION:For packet transfer from a central controller 6 to a communication controller CCE, control information, such as a packet coupling indication bit SYN, for indicating whether coupling with a next packet is required or not is added to the head of each packet, and the composite packet is transferred. The communication controller CCE controls the writing of packets to a packet storage memory 3 or the reading of packets from the packet storage memory 4 on the basis of the control information to perform packet synthesis processing. Therefore, a processing load on a central controller CPU is reduced to improve the efficiency of the packet synthesis.

Digital Microcommutators: Structure and Application

Abstract: Semiconductor technology achievements have opened up prospects for the development of integrated digital communication networks. Special LSI's have become a base element of communication means. Here, an approach is described for special LSI'sdesigned in the form of functionally complete communication systems of limited capacity-the microcommutators. The microcommutator contains all the subsystems of a switching system which thus make it possible to increase the switching system capacity by connecting the required number of microcommutators. The increase in microcommutator capacity can be achieved through the use of a space-time channel division structure. It is shown that the multistage space-divided microcommutators are preferable for the minimization of microcommutator nomenclature and the unification of a switching network of different capacity. An indication for the need for switching system synchronization is the shortage of space-divided switching networks based on space-time-divided microcommutators. An example of the performance of a local switching system with concentrators is given.

Route selecting system for packet exchange

Abstract: PURPOSE:To perform efficient packet transmission, by measuring a packet transfer time of a path to be detoured and selecting the optimum detour, when detour control is required. CONSTITUTION:Assuming that the transmission of information packet is made in a path 18 on a transmission line 10 between a transmission node 1 and an address node 2. If the selection of a detour is required due to a failure of the transmission line 10, the node 1 transmits a packet transfer delay time measuring packet to, e.g., a path 19. The nodes 2 and 3 act like a passing node to the said measuring packet and provide the passing time for the said packet. The measuring packet is returned to the node 1 via transmission lines 6, 8, 9 and 7. The node 1 measures the delay time of the measuring packet, and if the delay time is smaller than the reference value, this path is selected, and if larger, the similar measurement is made to other detours to select the detour.

Evaluation of advanced switching technologies for integrated voice/data applications

Abstract: I HIS paper is an exploratory evaluation of potential future switching technologies for integrated voice/data applications. The evaluation was for private line point-to-point ' applications based on future switching techniques that use activity compression' and presently tariffed transmission facilities including terrestrial and satellite-based private lines. Packet switching (PS), Hybrid switching (HS), and Digital Speech Interpolation systems (DSI), which use activity compression, are compared with the traditional Circuit switching system (CS), which does not use activity compression. Systems that use activity compression typically need a lower transmission bandwidth than those that do not (Le., CS) and, hence, they can be expected to save in transmission costs. However, because of increased processing at the switkh, switching costs for these systems are higher. The tradeoff between the transmission and switching costs are used to identify various potential regimes of usefulness for each switching technology. The regimes of usefulness are given in terms of the total traffic, the ratio of voice to data traffic, the internodal switch distances, and other parameters. The purpose of this paper is to illustrate the regimes and to highlight some of the important sensitivities. More detailed investigations need to be performed before any firm conclusions on switching technology comparisons can be made. The general setup for comparing the different systems is.a

FPSS - A Fast Packet Switching System

Abstract: FPSS is a local packet switching network connecting up to 256 computers or intelligent controllers. Transmission hardware is realized as a star network operating at an internal speed of 160 Mbit/s. Packet handling overhead is less than 3 usec per packet. The network software employs the virtual channel concept to provide data transmission between various sub processes on a time shared basis. The network operating program has been implemented as an extension of the SINTRAN III operating system of the NORD-100 computers used at DESY. A version for the PADAC microcomputer (TMS 9900) is under development.

Data transfer controlling system for loop-shaped common bus

Abstract: PURPOSE:To decrease the receiving time of a confirming packet at a transmitting node and at the same time to facilitate the data transfer procedure, by converting a transmitting packet into a confirming packet at a transmitting node and then transmitting the confirming packet after inserting the receiving result information into the final word. CONSTITUTION:A packet format is formed with a packet control word field A, a data word field B, a receiving result field C and an error detecting code field D. The data transmitted from a transmitting node 30 are fed and stored to a receiving node 8. Then a confirming signal transmitting circuit 5 is started, and the receiving packet is converted into a confirming packet. Then the results of a receiving information register 6 and an error detecting circuit 4 are inserted into the field C of the confirming packet. Furthermore a confirming packet added with the field D is transmitted to a common bus 1 through a driver circuit 7.