Showing papers on "Fault indicator published in 1986"

A Travelling Wave-Based Fault Locator for Two- and Three-Terminal Networks

Abstract: The high frequency components in fault waveforms present undesirable effects to most fault location algorithms and as a consequence filtering of postfault signals, to remove the high frequency transients, is essential for accurate fault location. A fault location algorithm that derives from travelling wave principles can cope with high frequency transients since these basically depend on travelling wave phenomena. The development of such an algorithm is the objective of this paper. Using the telegraph equations as a line model, voltage and current samples taken at one end of a line within the first 5 ms of fault inception are used to generate instantaneous voltage and current profiles for the rest of the transmission line. The voltage and current estimation is based on the solution of the equations of the line model by the method of characteristics. Criteria functions involving any of the square of the voltage, the square of the current, or the product of the two are applied for determination of the fault position. Fault position is given by the peak variation in tangent to the above basic functions. The algorithm finds application in fault location on two and three-terminal networks at both transmission and distribution levels.

Concurrent fault simulation for logic designs

Abstract: A system for concurrent evaluation of the effect of multiple faults in a logic design being evaluated is particularly useful in the design of very large scale integrated circuits for developing a compact input test set which will permit locating a predetermined percentage of all theoretically possible fault conditions in the manufactured chips. The system includes logic evaluation hardware for simulating a given logic design and evaluating the complete operation thereof prior to committing the design to chip fabrication. In addition, and concurrently with the logic design evaluation, the system includes means for storing large number of predetermined fault conditions for each gate in the design, and for evaluating the "fault operation" for each fault condition for each gate, and comparing the corresponding results against the "good machine" operation, and storing the fault operation if different from the good operation. By repeating the process on an event-driven basis from gate to subsequently affected gates throughout the design, a file of all fault effects can be developed from which an input test set for the logic design can be developed based on considerations of the required percentage of all possible faults to be detected and the time that can be allowed for testing of each chip. Special hardware is provided for identifying and eliminating hyperactive or oscillating faults to maintain processing efficiency.

Fault indicator having improved trip inhibit circuit

Abstract: A fault indicator for indicating the occurrence of a fault current in a monitored conductor includes an electrically actuated indicator flag. Trip circuitry within the fault indicator conditions the indicator flag from a normal reset-indicating state to a fault-indicating state upon the occurrence of a fault current in the conductor. Improved high impedance trip inhibiting circuitry inhibits the trip function following a loss of voltage in the conductor whereby the fault indicator is rendered insensitive to inrush current during a period immediately following restoration of power to the system.

Method and apparatus for isolating faults in a digital logic circuit

Abstract: The method and apparatus for isolating faults in circuitry of a digital computer includes the use of a fault isolation generation program which provides a data base containing a list of possible faulty components for each cycle of the computer's clock for execution by a service processor of the actual computer during testing. The fault isolation generation program is generated by using a simulator loaded with a mathematical model of the actual computer in connection with the execution of the diagnostic program executed on the actual computer during testing. The fault isolation program generates a list of circuit elements capable of generating fault indications, excluding circuit elements not capable of generating such fault indications.

LSI fault insertion

Abstract: Apparatus and method for providing programmable fault insertion circuitry in a large scale integrated (LSI) circuit device thereby eliminating the need for external switches or relays to create faults. A fault parameter word is stored in a register and the outputs of the register are decoded to select the fault condition to be inserted by an interfacing circuit to the logic being tested. Test vectors and the fault parameter word are generated by a controller coupled to the integrated circuit and a test response from the integrated circuit is examined by the controller.

Fault detection device for thermal printing head heating circuits

Abstract: A thermal printer with a fault detection circuit for detecting faults in heating elements used in the printer includes a print head containing the heating elements and a heating circuit associated with each element, a power supply, and a switching circuit interposed between the power supply and the print head. The fault detection circuit includes a current supply circuit, preferably a constant current source, which is connected in parallel to the switching circuit. A control circuit selects either a normal printing mode or a print head fault detection mode. In the fault detection mode, the switching circuit is disabled enabling the fault detection circuit to pass a test current through each of the heating elements for detecting any faults therein.

Digital fault locator

Abstract: A digital fault locator of this invention comprises a memory for storing input electric amount from a system and a plurality of digital filters having different filter functions to which electric amounts are supplied from the memory. A fault location is determined by selectively providing a specific one of outputs from the digital filters according to a fault time.

Directional comparison blocking system

Abstract: An echo-keyed directional comparison blocking system for protecting an electrical power transmission path in a power system network against internal faults is disclosed. The system includes a terminal unit disposed at each end of the transmission path for measuring characteristics representative of the power at its corresponding end and for activating a corresponding circuit breaker when an internal fault of the transmission path is detected. Each terminal unit includes a transmitter and a receiver for communicating transmit and receive signals with each other through a communication medium and additionally includes at least one forward-looking pilot relay, at least one over-current relay, and a plurality of circuits. The aforementioned combination provides for internal fault preference over an external fault, speeds up tripping of the circuit breakers under the conditions of one relay responding slower to a fault detection than another, eliminates problems which may delay circuit breaker activation caused by electrical noise coupled to the receiver, and improves transient block and unblock responses to fault conditions of the power system network.

Protective relay for an electric power system including decision-making computer means

Abstract: A protective relay for use in deciding an operating condition of an electric power system with a digital computer and protecting equipment connected to the electric power system. Basically, the protective relay is required to operate under an internal fault and not to operate under an external fault. The protective relay has a first comparison and decision element for determining whether the fault is an internal fault or an external fault by comparing a ratio between a vector summation (actuating quantity) and its maximum value (restraining quantity) in respect to an instantaneous electric current in the system. A second comparison and decison element decides whether the system is in a fault condition or not by detecting the actuating quantity in reference to its level with an output of the second comparison and decision element being inhibited by the output of the first comparison and decision element. The external fault is instantaneously judged by the first comparison and decision element and if a current transformer becomes saturated under the external fault and an excessive actuating quantity is generated, the relay is constructed with a return timer or a memory of the restraining amount in such a way as to continue inhibiting the second comparison and decision element to inhibit an erroneous operation of the protective relay.

Redundant digital distance relay

Abstract: A method and a device in connection with digital distance relays for obtaining a backup function in the event of faults in the digital signal processing and/or in the event of faults detected during automatic testing. The method comprises testing the distance relay continuously, in case of a faultless network, with respect to the digital signal processing by means of a central control unit. In case of a characteristic fault on the network, the distance relay is switched over from testing to protective function involving measurement by means of measurement signal units included in the distance relay. In case of a fault on the network and a simultaneous fault in the digital signal processing, fault signals from the measurement signal units, via time delay circuits and logical elements, bring about tripping of the line section subjected to the fault. When a fault is detected in the digital signal processing, an alarm function is triggered.

Mixed-Level Fault Coverage Estimation

Abstract: A Fault coverage estimation technique for mixed-level circuit is described. Observability formulae for combinational multiple-input multiple-output functional block are derived. Special procedures for estimating CMOS circuit transistor fault detection probability are developed, and the implementation of a FAult Coverage Estimation (FACE) system is described.

Method and evaluation component for determining high-frequency (radio-frequency) fault currents

Abstract: The invention relates to a method for determining an uncontrolled current (fault current) when feeding high-frequency energy to a body which is mounted on a frame, for example a table, which is earthed via an earthing line, in particular for the purpose of high-frequency surgery, according to which the fault current is measured by means of an evaluation component and, when a basic value is exceeded, a fault current signal is output.

Power System Ground Fault Current Distribution Using the Double-Sided Elimination Method

Abstract: One of the most frequent faults in power systems is the single line-to-ground fault. During such an event, large fault current circulates through the system, grounding network and the earth, returning to generating sources. It is this type of fault that is being referred to in this paper as ground fault or, simply, fault. Considering a power system of a relatively simple network configuration, and using the double-sided elimination method, direct solution for the fault current and its distribution among neutral conductors and the earth is derived. The entire faulted subsystem is modelled considering its grounding network as an integral part. The solution is general and the computer memory and time requirements are very modest. A parametric analysis was carried out to investigate the effect of various factors on the ground potential rise caused by the fault current.

Information data output device for electric-power systems

Abstract: According to the present invention, a sampled value of a reference voltage Vp which is a voltage (in general, a relative voltage to ground, an interphase voltage or a positive sequence voltage) prior to the occurrence of a fault in an electric-power system and a sampled value of the quantity of electricity E (a voltage or current in each phase or a symmetrical component voltage or current) during a fault time period or after the recovery of a fault are used to compute a plurality of functional values capable of specifying the phase angle θ or the value of θ of said quantity of electricity E in relation to said reference voltage Vp and deliver them as information data. When the relative phase angle between the quantity of electricity E during a fault or after the recovery of a fault and a voltage (reference voltage) Vp prior to the occurrence of a fault is clarified in this manner, the relative phase angles of reference voltages Vp among a plurality of electric stations prior to the occurrence of a fault are computed by obtaining the information of normal operating conditions of the electric power system concerning to a voltage, current, reactive power and the state of a circuit breaker and accomplishing the arithmetic operations of the information thus obtained and the constants of devices and equipment constituting the electric-power system. Therefore, the relative phase angles of the quantity of electricity E among a plurality of electric stations during a fault period or after the recovery of a fault can be clarified.

Elimination algorithm: a method for fault diagnosis in combinational circuits based on an effect-cause analysis

Abstract: In the paper we develop an approach to fault diagnosis in combinational circuits yielding a new method based on an effect-cause analysis. In our method the circuit under test N* is studied by using a description of its behaviour called the operation map. Depending on the set of tests applied, this description may allow the fault in N* to be detected before, and independently of, being located. The elimination of inputs in the operation map allows us to find the fault situations in N* (causes) which are compatible with the applied test and the obtained response (the effect). The method presented does not require a fault dictionary, fault enumeration or knowledge of the values expected in the fault-free circuit, and it makes possible applications such as obtaining faults not detected by a given test (including redundant faults), the identification of faults which cannot be modelled as stuck-at faults and other applications characteristic of this type of analysis.

Fault Contrast: A New Voltage Contrast VLSI Diagnosis Technique

Abstract: Fault contrast is a differential analog technique that yields high-quality voltage contrast images of integrated circuit (IC) pass vs. fail operation. Fault contrast is applicable where the IC failure mode is sensitive to an external parameter, e.g. clock frequency or supply voltage. Fault contrast requires only simple and inexpensive analog signal processing. We demonstrate fault contrast with an analysis of an Intel 80286 microprocessor failure.

Failure Analysis of Components Due to 480-V Ground Faults

Abstract: While many preferred methods exist for protecting components against damage from ground fault currents on 480-V systems, few analyses (if any) have been made concerning the effects on components (molded-case breaker, overload relay, etc.) due to a failure or absence of a ground fault protective device to clear a ground fault. Unlike fuses, which by definition could be considered self-protecting, no such feature exists in relays, molded-case breakers, or overload relay heater elements. The need for sensitive ground fault protection is clarified as by using known I2t techniques to examine the circuit components.

Device for an electronic fault detection, especially for the engine electronic in cars.

Abstract: In a device for electronic fault indication, especially for the engine electronics in motor vehicles, a fault detection circuit arrangement (11) and a fault encoder (13) which encodes output signals of the fault detection circuit arrangement into displayable fault numbers are provided. For fault indication, an on-board computer (7) with a display part (8) which normally serves for displaying operational data of the motor vehicle such as the engine speed or fuel consumption is used. For the fault display, the on-board computer can be switched to a converter (15) which converts the encoded fault signals into simulated operating signals which can be processed and displayed in the on-board computer. On the other hand, the on-board computer is normally connected to the output of the operating signal and actuating variable former (5).

A New Component Method for Fault Analysis in Three Phase Power Systems

Abstract: A new component method is developed to solve unbalance problems in power systems by substituting θ = 45° in Park's Transformation. Interconnection of sequence components network to simulate various shunt and series faults are obtained. The interconnected networks are similar to those obtained by symmetrical component transformation without any phase shifters.