Showing papers on "Fault model published in 1980"

Test Generation for Microprocessors

Abstract: The goal of this paper is to develop test generation procedures for testing microprocessors in a user environment. Classical fault detection methods based on the gate and flip-flop level or on the state diagram level description of microprocessors are not suitable for test generation. The problem is further compounded by the availability of a large variety of microprocessors which differ widely in their organization, instruction repertoire, addressing modes, data storage, and manipulation facilities, etc. In this paper, a general graph-theoretic model is developed at the register transfer level. Any microprocessor can be easily modeled using information only about its instruction set and the functions performed. This information is readily available in the user's manual. A fault model is developed on a functional level quite independent of the implementation details. The effects of faults in the fault model are investigated at the level of the graph-theoretic model. Test generation procedures are proposed which take the microprocessor organization and the instruction set as parameters and generate tests to detect all the faults in the fault model. The complexity of the test sequences measured in terms of the number of instructions is given. Our effort in generating tests for a real microprocessor and evaluating their fault coverage is described.

A stochastic fault model: 1. Static case

Abstract: The number-size distribution of earthquakes requires that irregularities exist on a fault at all length scales. The assumption of self-similar irregularity is used to formulate a stochastic description of the faulting process. A random irregularity is termed self similar if it remains statistically similar upon a change of length scale. Self-similar geometric irregularity of a fault surface is represented in this model by stress and friction functions that fluctuate self similarly on a plane. If the set of rupture areas of all earthquakes on the brittle portion of a fault plane is assumed to be self similar, then the number of ruptures with area greater than A is proportional to 1/A. If stress drop is independent of earthquake size, then the number of earthquakes with moment greater than M/sub 0/ is proportional to M/sub 0//sup -2/3/. The size of an earthquake is determined by spatial fluctuation of the initial stress and sliding friction functions. The spectrum of the stress function is related to both the average stress drop as a function of earthquake size and the number-moment distribution. A model of the slip and stress change functions of an earthquake is constructed in the Fourier transform domain. While the stressmore » function becomes smoother in an earthquake at the length scale of the rupture, it becomes rougher at shorter length scales to prepare the fault for future smaller earthquakes. Seismicity is a cascade of stored elastic energy from longer to shorter wavelengths.« less

Fault Diagnosis Based on Effect-Cause Analysis: An Introduction

Abstract: This paper presents the basic concepts of a new fault diagnosis technique which has the following features: 1) is applicable to both single and multiple faults, 2) does not require fault enumeration, 3) can identify faults which prevent initialization, 4) can indicate the presence of nonstuck faults in the D.U.T., 5) can identify fault-free lines in the D.U.T. Our technique, referred to as effect-cause analysis, does not require a fault dictionary and it is not based on comparing the obtained response of the D.U.T. with the expected response, which is not assumed to be known. Effect-cause analysis directly processes the actual response of the D.U.T. to the applied test (the effect) to determine the possible fault situations (the causes) which can generate that response.

Diagnosis Without Repair for Hybrid Fault Situations

Abstract: For a new class of fault situations called hybrid fault situations, we consider the fault diagnosing capabilities of systems which for testing/monitoring purposes can be viewed as being composed of independent units. The classical Preparata, Metze, and Chien model (PMC model) is used to specify the various testing assignments among the units. Hybrid fault situations are described as explicitly bounded combinations of permanently and intermittently faulty units. This new concept of a hybrid fault situation includes as special cases the all permanent fault case and the unrestricted intermittent fault case which have both been previously considered with PMC models. A general characterization of the so-called connection assignment of a PMC model is established for a diagnosing capability which is referred to as hybrid fault diagnosability without repair. This diagnosing capability is compatible with the well-known permanent fault diagnosability without repair concept, and the quality of this diagnosing capability is shown to be correct, but sometimes an incomplete diagnosis where the incompleteness is solely a consequence of intermittently faulty units. The characterization for hybrid fault diagnosability without repair is seen to encompass as extreme cases the previously known special characterizations for permanent and unrestricted intermittent diagnosability without repair. Fundamental interrelationships are determined among parameter bounds used to describe the hybrid fault cases which can be diagnosed for a given PMC model.

Quasi-static deformations due to an inclined, rectangular fault in a viscoelastic half-space

Abstract: Analytical expressions of the quasi-static, surface deformations (displacement, strain and tilt) due to an inclined, rectangular fault in a viscoelastic half-space are obtained by applying a "correspondence principle" to the solutions of the associated elastic problem. The medium is assumed to be elastic dilatational and Maxwell deviatric, and the time dependence of a dislocation source is taken to be of a step function type.From the analytical expressions, it is directly found that the viscoelastic part of the deformation field vanishes exactly for both an arbitrary slip on a horizontal fault plane and a dip-slip faulting on a vertical plane. In other cases, the viscoelastic part has a time dependence prescribed by a factor, 1-exp(-t/τ), where τ denotes the relaxation time determined from the Lame's elastic constants and the viscosity of the medium.Patterns of the elastic and the viscoelastic parts of the deformation field are respectively shown for two representative fault models. As an example, postseismic vertical displacements associated with the Kanto earthquake of 1923 are computed by the fault model determined from the coseismic geodetic data, and compared with the observed crustal movements for the period of 1931-1950.

Decomposition Methods for Fault Tree Analysis

Abstract: Some kinds of fault tree analysis are described for which cut set enumeration is inadequate. Modularization leads to more efficient computer programs, and also identifies subsystems which are intuitively meaningful. The problem of finding all modules of a fault tree is formulated as as extension of the problem of finding all ``cut-points'' of an undirected graph. The major result is a FORTRAN program (available as a Supplement) which can find modules of a 1000-event fault tree in a small fraction of a second. A generalized module is defined.

Identification of Equivalent Faults in Logic Networks

Abstract: The properties of combinational logic functions and networks that influence equivalence among stuck-type faults are investigated. It is shown that the equivalence of certain types of faults depends only on the function being realized. For instance, the fault classes among primary input/output faults are of this type. It is shown that every irredundant realization of the two-variable EXCLUSIVE-OR function has a unique set of ten fault classes. A fault class F in a module M contained in a network N is called intrinsic, if F can be determined from M alone, i. e., F is independent of N. Using the concepts of intrinsic equivalence and inversion parity, conditions for the equivalence and nonequivalence of two fault classes are obtained. These results are applied to the problem of equivalence identification in two-level logic networks where they provide a substantial reduction in the amount of computation required.

Fault tolerance of a class of connecting networks

Abstract: Several proposals have been made for using a class of connecting networks called b-networks in multicomputer systems, such as systems containing large numbers of microprocessors. A b-network is a network of 2 × 2 crossbar switches called b-elements. This paper presents an analysis of the fault tolerance of b-networks intended for multicomputer applications. A fault model is used which allows b-elements to be stuck in either of their two normal states. A new connectivity property called dynamic full access (DFA) is introduced which serves as the criterion for fault tolerance. A b-network is said to have the DFA property if each of its inputs can be connected to any of its outputs in a finite number of passes through the network. A fault is called critical if it destroys the DFA property. Two graph-theoretical characterizations of the critical faults of a b-network are presented. It is shown that there is a one-to-one correspondence between minimal critical faults and the cutsets of the circuit adjacency graphs derived from the b-network. It is further shown that a fault is critical if and only if it is incompatible with all Eulerian circuits associated with the b-network. Some applications of the theory are discussed.

Design of Totally Fault Locatable Combinational Networks

Abstract: The design of combinational logic networks is considered in which equivalent or indistinguishable stuck-type faults are confined to a small region of the network. A general type of fault equivalence called S-equivalence is introduced, which defines fault equivalence with respect to an arbitrary set of modules S. A network N is called totally fault locatable with respect to module set S, denoted TFLS, if all specified faults in N are S-equivalent. Some general structural properties of TFLS networks are derived. The problem of designing TFLS networks is investigated for S = {AND, OR, NAND, NOR, NOT} denoted AON, and S = {AON, EXCLUSIVE- OR} denoted AONE. All equivalent fault classes in TFLAON and TFLAONE networks can be identified by inspection. It is shown that every function has a TFLAONE network, that is, a realization where all equivalence classes can be identified by inspection, containing at most one control point or extra input. A method for constructing a TFLAONE realization of an arbitrary function is presented using at most one control point.

An Optimized ATPG

Abstract: This paper describes a hierarchical approach to the detection of the critical faults of a digital board, i.e., those most likely to occur. The failure probabilities of the nodes of a board are estimated and used as weights in selecting the nodes for fault detection. The study has indicated both a saving in pattern generation and a higher fault detection per pattern. This approach introduces a new definition of fault coverage. The approach is also applicable to analog circuits. In addition, it allows for continual incorporation of field data, thus improving the estimation of the failure probabilities.

Fault tolerance in packet communication computer architectures

Abstract: It is attractive to implement a large scale parallel processing system as a self-timed hardware system with decentralized control and to improve maintainability and availability in such a system through fault tolerance. In this thesis we show how to tolerate hardware failures in a self-timed hardware system with a packet communication architecture, designed to execute parallel programs organized by data flow concepts. We first formulate a design methodology for incorporating redundant hardware into self-timed systems for fault tolerance. Redundancy management problems in self-timed systems are illustrated with a byte-sliced hardware module structure. Robust algorithms are given for synchronizing byte slices in a redundant module so that their outputs can be decoded to detect and/or mask hardware failures. Hardware implementation of these redundancy management algorithms is studied under a stuck-at fault model, a random pulse train fault model and a random wave train fault model. In studying the design of fault-tolerant data flow processors we have also developed a dynamic redundancy scheme for masking hardware failures in a multiprocessor architecture designed to execute parallel programs organized by data flow principles. Novel features of this architecture include use of packet networks to support communication among processing elements and dynamic allocation of a homogeneous set of functional units to service requests. Program organization and hardware module designs to support the dynamic redundancy scheme are described.

Fault detection in combinational circuits using a compressed fault table

Abstract: A method is developed for obtaining a highly compressed fault table for two-level combinational circuits. A set of operations is defined through which the minimal test set for detecting stuck-at faults is obtained from the compressed fault table. The method is equally suitable for sum of products form or product of sums form realization of logic functions and generates the test set directly from the algebraic expression of the logic function.