Showing papers on "Flip-flop published in 1969"
Patent•
13 Mar 1969TL;DR: In this paper, a master slave flip-flop including two bistable logic stages, each of which includes transistors which are crossconnected to alternately conduct as binary information is applied to the stages.
Abstract: Disclosed is a master slave flip-flop including two bistable logic stages, each of which includes transistors which are crossconnected to alternately conduct as binary information is applied to the stages. Both logic stages are connected to receive clock signals which enable binary information to be applied to and stored by one of the two logic stages and thereafter shifted into the other stage when the level of clock signals changes.
11 citations
Patent•
12 Nov 1969TL;DR: In this article, the authors proposed an approach to solve the JK-type FLIP-FLOP problem using only direct-coupleded logic gates, which can be used to simulate a state response.
Abstract: UNLOCKED JK-TYPE FLIP-FLOP USING ONLY DIRECT-COUPLED LOGIC GATES. ACTIVATING SIGNALS APPLIED TO EITHER OF TWO INPUTS CAUSE THE FLIP-FLOP TO ASSUME A STATE CORRESPONDING TO THE ACTIVATED INPUT. ACTIVATING SIGNALS APPLIED TO BOTH INPUTS SIMULTANEOUSLY CAUSE THE FLIP-FLOP TO CHANGE STATE.
9 citations
Patent•
26 Nov 1969
TL;DR: In this paper, a noise immune data processing flip-flop circuit arrangement is described, in which the clock input for one or more transition triggered flipflops is fed to the NAND circuit via a resistor until an input pulse for triggering appears which has at least a given duration.
Abstract: A noise immune data processing flip-flop circuit arrangement is described in which the clock input for one or more transition triggered flip-flops is fed to the clock input terminal of respective flip-flops via a NAND circuit means which prevents the start of charging of a capacitor, across which triggering voltage is to appear, via a resistor until an input pulse fed to the NAND circuit appears which has at least a given duration thereby making the flip-flop immune to noise pulses of shorter duration. Additionally, the pulse for triggering must have a still greater duration sufficiently long enough to allow the capacitor to reach the transition voltage level for the flip-flop providing further protection from false triggering by noise pulses of still greater duration than the given duration. The clear input for the flipflop is also provided with NAND circuit means, and the Q and Q outputs from the flip-flop are fed to NAND circuits which are connected to a single voltage supply source via resistors.
8 citations
Patent•
09 Dec 1969TL;DR: A master slave flip-flop having lower dissipation and for a reduced number of cross-overs by the use of inverse logic, with a correct choice of the length width ratios of the channels of the field effect transistors in order to prevent untimely changes of state are prevented.
Abstract: A master slave flip-flop having lower dissipation and for a reduced number of cross-overs by the use of inverse logic, with a correct choice of the length width ratios of the channels of the field-effect transistors in order to prevent untimely changes of state are prevented.
7 citations
Patent•
15 Jan 1969
TL;DR: A flip-flop circuit is a circuit with a feedback path which stabilizes the output when both set and reset input signals are applied to the input of the circuit as mentioned in this paper.
Abstract: A flip-flop circuit particularly useful in connection with integrated circuitry and embodying a feedback path which functions to stabilize the output when both set and reset input signals are applied to the input of the circuit.
7 citations
Patent•
22 Jan 1969TL;DR: In this paper, a J-K master-slave flip-flop with improved internal propagation and drive characteristics is realized in monolithic integrated form by utilizing current steering to control slave switching.
Abstract: A J-K master-slave flip-flop having improved internal propagation and drive characteristics is realized in monolithic integrated form. Improved internal signal propagation is achieved by utilizing current steering to control slave switching. Drive requirements are minimized by using input gates which are fabricated on the monolithic chip.
6 citations
Patent•
13 Jun 1969TL;DR: In this article, a flip-flop circuit consisting of a slave circuit formed of a pair of cross-coupled MOSFETs and a master circuit connectable to the slave circuit by the trigger pulse is disclosed.
Abstract: A MOSFET flip-flop circuit consisting of a slave circuit formed of a pair of cross-coupled MOSFETs and a master circuit connectable to the slave circuit by the trigger pulse is disclosed. Precharging of the slave and master circuits can be accomplished by a system clock or by DC. By substituting an analog voltage for the precharging voltage on one or both sides of the master circuit, the output pulse length and output pulse interval can be separately regulated over a considerable range of integral numbers of trigger pulses. Several flip-flop circuits can be connected through MOSFET gates to produce a binary counter.
5 citations
Patent•
[...]
TL;DR: In this paper, a JK-flip-flop of the master-slave type where the output signals from the slave flip-flops are each fed back to a separate input gate each consisting of separate partial gates.
Abstract: A JK-flip-flop of the master-slave type wherein the output signals from the slave flip-flop are each fed back to a separate input gate each consisting of separate partial gates. The J and K signals are both fed to each of the input gates whereby changes in the J and K signals occurring during a clock pulse are registered in the slave flip-flop.
5 citations
Patent•
16 Apr 1969
TL;DR: In this paper, a bistable flip-flop is set and reset respectively by two signals whose phases are to be compared and provides pulses of width determined by the phase difference, in order to prevent erroneous indication of phase synchronism when one signal frequency is an integral multiple of the other.
Abstract: A bistable flip-flop is set and reset respectively by two signals whose phases are to be compared and provides pulses of width determined by the phase difference. In order to prevent erroneous indication of phase synchronism when one signal frequency is an integral multiple of the other, a frequency comparator blocks the flip-flop when the frequencies are different and itself provides the said pulses, instead of the flip-flop.
2 citations