Showing papers on "Flip-flop published in 1975"

A flip-flop and logic gate with Josephson junctions

Abstract: A complementary logic circuit with Josephson junctions has been investigated theoretically and experimentally. This paper will discuss a circuit with a measured risetime of 100 ps, a power dissipation of 16.4 μW, with the flip-flop operated with a 1500-MHz input signal.

Binary voltage-differential sensing circuits, and sense/refresh amplifier circuits for random-access memories

Abstract: In one example, a generally conventional flip-flop circuit is used, including a pair of input field-effect transistors having their gates connected respectively to a pair of circuit nodes A and B. During a preset portion of the cycle, both nodes A and B are preset to an initial reference potential V R , set so that the transistors turn partially ON and act as variable resistors. Thereafter, an unknown voltage V X to be sensed is connected to node A, V X being equal to V R ± ΔV. The flip flop then responds to differential conductivity between the transistors, to produce a binary output voltage at one of two levels set by the sense of ΔV, plus or minus. In a semiconductor RAM circuit, selected memory cell capacitors are connected in sequence to node A, and the flip-flop circuit senses the cell charge and produces an amplified output representative thereof, which is later fed back to the memory cell to refresh the charge originally stored therein.

Flip-flop false output rejection circuit

Abstract: An asynchronously timed digital flip-flop circuit eliminates malfunction occurring when internal race conditions cause the flip-flop to lock up at the guasi-stable threshold state in which both input and output signals of the flip-flop are not at true logic levels but are equal to each other. The addition of special circuitry to reject these "false" outputs eliminates their propagation in the digital system in which said flip-flop is employed.

Complementary Josephson-junction circuit: a fast flip-flop and logic gate

Abstract: A logic circuit with Josephson junctions has been developed that operates as logic gate or as a flip-flop. Despite the latching-type characteristic of the Josephson tunnel junction, the complementary logic circuit is nonlatching. The test circuit has a power dissipation of 16.4 μW and a signal risetime of approximately 60 ps has been measured.

Regulated transistorized DC to DC converter and parallel operation of plurality of converters

Abstract: Various types of static DC to DC converters are known. Some of these have output rectifiers including phase controlled SCRs. The present invention eliminates the need for controlled output SCRs by pulse width modulation of switching elements in a control circuit controlling the converter circuitry itself. This results in the elimination of some switching devices, higher reliability and higher-efficiency, A unijunction oscillator drives a one-shot multivibrator and a flip flop. The unijunction oscillator, one-shot multivibrator and flip flop feed two AND gates which are alternately enabled to allow pulses of current to flow from a DC source through opposite halves of a primary winding of a transformer. The output of the secondary winding is rectified and filtered to provide the converter output. Voltage regulation is accomplished by controlling the one-shot multivibrator. In one embodiment, paralleling of a number of converters is enabled by providing for frequency and pulse width synchronization.

Noise immunity cct. for circuits exposed to noise from contact chatter - has two bistable flip-flops to suppress noise during clock pulses

Abstract: The noise immunity circuit, for protecting electronic circuits that are susceptible to noise (causing erroneous switching etc.) from contact chatter, has the signal (A) containing the noise applied to a bistable flip flop (13). The flip flop outputs are passed over logic circuits (14 16) to a second bistable flip flop (17) to suppress noise that occurs during the clock pulses (B) of both flip flops. The noise-free signal (H) is taken from the second flip flop's output. the logic circuit contains an equivalence gate (14) to recognise equal states at the first flip flop's input and output. Two AND-gates (15, 16) are connected between this equivalence gate and the second flip flop.

Five gate flip-flop

Abstract: A JK flip-flop circuit comprising four multiple input gates having each output fed back to an input to each gate of an opposite pair of said four gates; a clock pulse shaping circuit is provided when triggering clock pulses are to be of unknown shape or duration or when the clock pulses to be supplied are of a duration longer than twice the propagation delay time of the slowest gate of the circuit.

A ternary flip-flop circuit

Abstract: The paper describes a Ternary flip-flop. The output is obtained in the form of three: levels of voltage corresponding to logic status 2, 1, 0, when triggered by 1 kHZ pulses.

Bipolar memory cell employing inverted transistors and pinched base resistors

Abstract: A bipolar random access memory cell is disclosed using a pair of transistors cross-coupled in a flip flop configuration with the transistors connected to operate in the inverted mode, that is, the collectors as emitters and the emitters as collectors. This allows an integrated circuit realization of a random access memory having only one and one-half isolation regions per row of memory cells. Forming the flip flop load resistors by the emitter-pinched base method compensates the cell for process variations to result in substantially constant read/write characteristics.

Pulse cct. responding to magnetic tape markings - supplies digital pulse train representing optical markings of differing width

Abstract: The reverse side of the magnetic tape carries groups of code markings in the form of long and short printed stripes, which represent a binary number. These are detected by optical reading means connected to a logic circuit, supplying pulses to an analysis unit via which a chosen tape position may be obtained. The optical reading means respectively supply timing pulses and code pulses both, being supplied to the logic circuit. This comprises an OR gate and an AND gate in parallel, with the gates connected to the control inputs of a flip-flop. The output voltage of the OR gate and the flip flop are used as the timing pulses and the code pulses for controlling the analysis unit.

Acoustically-triggered switching circuit - has microphone operating flip-flop with delay circuit containing photocell to maintain stair lights

Abstract: The acoustically-triggered switching circuit has a microphone passed over an amplifier to a rectifier. The rectifier output is passed over a pulse shaper to a flip-flop acting as a memory. The bistable flip-flop operates the relay thyristor or triac that switches the load in or out. The bistable flip-flop has a timing circuit containing a photocell and a trigger. The timing circuit holds the 'switch' closed for a given time. The switching circuit is used, for example, with stair lights or other optical systems which can then be turned on by a noise and turn themselves off automatically after the time delay has elapsed.

Regenerating and rating circuit of keyed flip-flop type - has two integrated inverting amplifier stages and gate electrodes of different materials

Abstract: The amplifier stages each consist of a switching transistor nodes of the regenerating circuit. The switching transistors are so rated that their starting potential corresponds to the most favourable average value UM = 0.5. (UBO + UB1). The starting potential of the switching transistors can be (+-) 20% of the most favourable average value UM. The gate electrodes of the load transistors and switching transistors are made of different materials, the work function between the gate electrode material and the sub-layer of the switching transistors being greater than the corresponding work function of the load transistor.

Electronic motor overload protection cct. - monitors machine's temp. and has cut-out operated by bistable flip-flop and measured value generator

Abstract: To the bistable flip-flop is connected a tripping circuit. The flip flop is formed by a bistable storage element whose amplified, converted output operates the motor cut-out relay when energised by a current voltage or light pulse independently of external source. The storage element is programmable and may be of electromagnetic type with two stable states, of magnetic tape with a magnetisable core of electric type, such as a capacitor or superconducting ring, or of chemical type.

Phase detector for digital signals - reference and feedback frequency signals are summed in flip-flop

Abstract: A phase detector circuit operates to close the loop around a voltage controlled oscillator so that the operating frequency is maintained constant and in agreement with a reference frequency signal. A main control stage consists of a flip-flop conditioned by a reference input frequency of square wave form and a feedback frequency from the oscillator output. The duty cycle of the flip-flop outputs is dependent upon the phase difference. The outputs are fed to power stages that operate gates coupled to and output line that contains an integrating circuit. The variable pulse width output is integrated to provide an output proportional to phase difference over a range of (+-) 180 deg. A second control circuit flip-flop provides compensation in the event that a reference pulse is dropped.

Delayed switching through a D.C. voltage - has electronic switch flip-flop with two differential inputs and two RC circuits

Abstract: The electronic swtich, e.g. a thristor, is controlled by the flip flop. the R.C. junction points of the R.C. circuits are connected to the flip flop differential inputs. Stationary capacitor voltage and time constant of the first R.C. circuit are smaller than those of the second R.C. circuit. If the flip flop has one transistor, the differential inputs are connected to the transistor base and emitters. If the flip flop has two transistors, the second transistor base is connected to the first transistor collector, and its collector to the first transistor base.