Showing papers on "Gate driver published in 1978"

HF Amplifier circuit

Abstract: A high frequency input signal is applied to one gate of a dual gate MES or MIS field effect transistor. A high gain control voltage is applied to the second gate. To reduce the steepness of the main control slope in the pinch-off voltage region of the transistor a diode combination is connected between the second gate and a node of the amplifier circuit which has a fixed potential lying within the gain control voltage range. The conductive threshold of the diode combination is selected such that the combination becomes conductive when the gate control voltage is sufficient to initiate pinch off of the field effect transistor. The diode combination suitably may comprise a forward conduction diode connected a series opposed polarity with a zener diode or, alternatively, may comprise a series chain of forward conduction diodes.

Transistorized power amplifier

Abstract: A transistorized power amplifier includes a differential pair coupled to a push-pull driver. The latter provides an amplified signal to an output stage through a compound driver, which comprises a pair of complementary transistors. The collector of the input transistor of the compound driver is connected to the base of the other transistor in the compound driver.

Laser cut storage cell

Abstract: Use of a residual charge bleed-off diode connected to the gate of an FET device in a Read Only Storage (ROS) is disclosed. The ROS is personalized by cutting selected gate leads in an array of FETs with a laser beam. Experience has shown that static electric charges on the lead due to handling prior to cutting become isolated at the gate after the gate lead is cut, producing an unpredictable conduction state for the FET instead of a solid off-state as desired. By providing a bleed-off diode which remains connected to the FET gate after the cut is made, the charges are allowed to leak away from those FETs whose gates have been cut while, at the same time, preventing the voltage of the FET gate from floating. The diode is oriented so as to offer a high impedance to current flowing from the gate node when the gate is biased for FET conduction. This minimizes the effect of the diode on circuit speed when the gate remains connected with the balance of the read only storage circuitry. If the gate and diode have been selectively severed from the balance of the read only storage circuitry, in the course of programming the storage, any residual charge on the gate is conducted through the diode by virtue of its reverse bias leakage or forward biased conduction state, depending upon the polarity of the residual charge on the gate.

Column decode circuit for random access memory

Abstract: Disclosed is column decode circuit for a random access memory, which column decode circuit is comprised of a conventional transfer gate transistor, conventional driver transistors and a conventional load transistor. The column decode circuit further includes a chip enable gate transistor according to the present invention. The conventional gate transistor transfers data stored in a corresponding memory cell of the random access memory in accordance with a column address information. The column address information received by the conventional driver transistors connected in parallel causes the above gate transistor to be conductive or nonconductive. Accordingly, the conventional load transistor will apply a voltage of a particular voltage level (Vcc) from a voltage supply to the gate of the transfer gate transistor. The chip enable gate transistor, the load transistor and the parallely connected driver transistors are all connected in series. The thus connected column decode circuit has a very low power consumption and a high speed operating capability.

Circuit arrangement for compensating the change in input capacitance at a first gate electrode of a dual-gate MOS field-effect transistor

Abstract: In an insulated gate field effect transistors having two gate electrodes, the drain-source current can be controlled by voltages applied at the two gate electrodes. Changes in the input voltage at one gate electrode are accompanied by a change in the input capacitance at the other gate electrode causing a change in load impedance for the source controlling this gate electrode which can give rise to undesirable reactions on the source. A source resistance in the form of a voltage divider has a tap which is connected to the second gate electrode. By proper dimensioning of the voltage divider, the gate-source voltage at the first gate electrode can be made to change, in the event of a change in the input voltage applied to the second gate electrode, by an amount sufficient to counteract any undesirable change in the input capacitance at the first gate electrode.