Showing papers on "Hardware register published in 1993"

Detecting unauthorized modification of communication unit based on comparison between stored hardware identification code and hardware identification code generated from operational platform identification code

Abstract: A database unit monitors the communications occurring within at least one communication system for hardware identification codes of communication or broadcast units. Upon detecting the hardware identification code, the database unit compares the one received with a stored hardware identification code for the unit. When the stored hardware code does not match the one received, the database unit indicates that the unit has undergone an unauthorized modification.

Digital circuit design assist system for designing hardware units and software units in a desired digital circuit, and method thereof

Abstract: A digital circuit design assist system is directed to provide a system which independently verifies hardware divided into a plurality of units or the hardware and software, and reduces the design time. The system includes a functional model storage unit 1 for storing functional models in order to design hardware for a desired digital circuit including the hardware alone or the hardware and firmware, and functionally expressing the digital circuit by a hardware description language through a text editor 15 by coding input. Logic synthesis system 2 is provided for converting the functional model to a structural model, structurally expressed by the hardware description language. Structural model storage unit 3 is provided for storing the structural model, and a language model library storage unit 4 is provided for storing language models each expressing each of a plurality of components constituting the hardware by the hardware description language. Hardware description language simulation system 5 is provided for verifying correctness of the logic of the hardware from the functional model, the structural model and the language model.

Object-oriented system using objects representing hardware devices, physical connectors and connections between the physical connectors for configuring a computer

Abstract: An object-oriented hardware configuration system for enabling centralized user configuration of hardware in a computer system includes a plurality of object-oriented hardware interface objects each representing a hardware device physical connector, and a plurality of object-oriented hardware module objects. Each of the hardware module objects represents a hardware device that is user-configurable. Each of the hardware module objects includes one or more hardware interface objects associated with the hardware device such that connectors of the hardware device are defined. An object-oriented hardware configuration object is provided, wherein the hardware configuration object includes a plurality of hardware module objects that represent hardware devices connected to a particular computer system. The hardware configuration object defines a hardware configuration of the particular computer system. A user may access the hardware configuration object to configure the hardware devices connected to the particular computer system.

Generation of hardware machine models from instruction set descriptions

Abstract: The authors describe how a modular machine description, which specifies the functionality and the binary representation of an instruction set, can be transformed into a hardware model. This model is built from new generic hardware entities (registers, memories, arithmetic/logic operators, selectors and connections) and may eventually serve as an input to high-level hardware synthesis tools. The transformation steps on the way from the machine description to the hardware model are explained by giving an example. >

The next-generation SPARC multiprocessing system architecture

Abstract: The SPARCcenter 2000's multiprocessor architecture defines a set of functional building blocks that share a common hardware interface, the XDBus. This modular approach permits the implementation of multiprocessors covering a wide range of performance and cost. It allows the ratio of processing power, memory capacity, and I/O bandwidth to be varied within a given machine while permitting system designers to address different points on the overall performance spectrum. Each functional block (processor, memory, I/O) consists of a small number of highly integrated chips. The architecture provides a number of features to support high-performance symmetric multiprocessor software. These include hardware caches, TLB coherency, dynamic interrupt dispatching with source identification, weak write ordering, block copy hardware, and hardware performance monitoring. >

Shifting register windows

Abstract: Shifting register windows, a register windowing method that attempts to overcome some of the difficulties of traditional fixed- and variable-sized schemes, is described. Using fewer register elements than a seven-window Sparc organization, shifting register windows more than halves spill/refill memory traffic and reduces visible spill/refill cycles by an order of magnitude. In addition, shifting register windows, a scheme based on fast hardware stack and register-memory dribbling, has a very short register bus length. It also zeros registers as they are being allocated, making common initialization unnecessary. >

Fault information gathering system of information processor

Abstract: PURPOSE: To gather local memory information by the fault information gathering system of the information processor even if the local memory information on a faulty unit can be gathered through a system bus in the case that a fault relating to the system bus which occurs to the unit. CONSTITUTION: The hardware information gathering means 21 of a diagnostic processor 2 gathers hardware register information on the unit 3 where the fault occurs through a diagnostic bus 7 and a gathering possible/impossible judgement means 22 judges whether or not the local memory information on the faulty unit 3 can be gathered through the system bus 6 from the hardware register information. When the information can be gathered, a saving means 23 actuates the dump firmware of the faulty unit p3 to saves the local memory information on the faulty unit in a main storage device 1 through the system bus 6, but when the information can not be gathered, a local memory information gathering means 25 gathers the local memory information on the faulty unit 3 through the diagnostic bus 7. COPYRIGHT: (C)1994,JPO

Eliminating Higher-Order Quantifiers to Obtain Decision Procedures for Hardware Verification

Abstract: In this paper, we present methods for eliminating higher-order quantifiers in proof goals arising in the verification of digital circuits. For the description of the circuits, a subset of higher-order logic called hardware formulae is used which is sufficient for describing hardware specifications and implementations at register transfer level. Real circuits can be dealt with as well as abstract (generic) circuits. In case of real circuits, it is formally proved, that the presented transformations result in decidable formulae, such that full automation is achieved for them. Verification goals of abstract circuits can be transformed by the presented methods into goals of logics weaker than higher-order logic, e.g. (temporal) propositional logic. The presented transformations are also capable of dealing with hierarchy and have been implemented in HOL90.

Method and device for accessing hardware register

Abstract: PURPOSE:To directly access a hardware register from a program and to shorten time required for accessing by mapping the hardware register as data on a program on an operating system(OS). CONSTITUTION:The hardware register 2 is mapped as data on an application 3 by using a virtual storage function. A switch 4a which is cut at busy time is provided between the hardware register 2 and a bus 4. Since the hardware register 2 can directly be accessed from the application 3 without the aid of OS 1, time required for accessing can considerably be shortened. Furthermore, busy control is executed only when the hardware register 2 actually comes to a busy state, and therefore it is not necessary to sense the status of the hardware register. Then, required time as whole busy control can be shortened.

Diagnosis control system for peripheral controller

Abstract: PURPOSE: To extract scan path data of a hardware register from a host device without need of a maintenance diagnosis exclusive bus on the occurrence of a hardware fault in a peripheral controller during system operation. CONSTITUTION: On the occurrence of a hardware fault, a diagnosis control section 30 detecting the fault, scan path data of the hardware register are collected and stored in a memory section 10 and when the storage of all data is finished, a flag indicating the storage of the scan path data in the memory section 10 is set and interrupt is produced to a firmware. The firmware receiving an interrupt collects fault information to command resetting. A processor section 40 receiving the reset command initialize the controller and it is reported to a host device when the initializing is finished. COPYRIGHT: (C)1995,JPO