Showing papers on "Hardware Trojan published in 2009"

MERO: A Statistical Approach for Hardware Trojan Detection

Abstract: In order to ensure trusted in---field operation of integrated circuits, it is important to develop efficient low---cost techniques to detect malicious tampering (also referred to as Hardware Trojan ) that causes undesired change in functional behavior Conventional post--- manufacturing testing, test generation algorithms and test coverage metrics cannot be readily extended to hardware Trojan detection In this paper, we propose a test pattern generation technique based on multiple excitation of rare logic conditions at internal nodes Such a statistical approach maximizes the probability of inserted Trojans getting triggered and detected by logic testing, while drastically reducing the number of vectors compared to a weighted random pattern based test generation Moreover, the proposed test generation approach can be effective towards increasing the sensitivity of Trojan detection in existing side---channel approaches that monitor the impact of a Trojan circuit on power or current signature Simulation results for a set of ISCAS benchmarks show that the proposed test generation approach can achieve comparable or better Trojan detection coverage with about 85% reduction in test length on average over random patterns

Hardware Trojan: Threats and emerging solutions

Abstract: Malicious modification of hardware during design or fabrication has emerged as a major security concern. Such tampering (also referred to as Hardware Trojan) causes an integrated circuit (IC) to have altered functional behavior, potentially with disastrous consequences in safety-critical applications. Conventional design-time verification and post-manufacturing testing cannot be readily extended to detect hardware Trojans due to their stealthy nature, inordinately large number of possible instances and large variety in structure and operating mode. In this paper, we analyze the threat posed by hardware Trojans and the methods of deterring them. We present a Trojan taxonomy, models of Trojan operations and a review of the state-of-the-art Trojan prevention and detection techniques. Next, we discuss the major challenges associated with this security concern and future research needs to address them.

Hardware Trojan horse detection using gate-level characterization

Abstract: Hardware Trojan horses (HTHs) are the malicious altering of hardware specification or implementation in such a way that its functionality is altered under a set of conditions defined by the attacker. There are numerous HTHs sources including untrusted foundries, synthesis tools and libraries, testing and verification tools, and configuration scripts. HTH attacks can greatly comprise security and privacy of hardware users either directly or through interaction with pertinent systems and application software or with data. However, while there has been a huge research and development effort for detecting software Trojan horses, surprisingly, HTHs are rarely addressed. HTH detection is a particularly difficult task in modern and pending deep submicron technologies due to intrinsic manufacturing variability. Our goal is to provide an impetus for HTH research by creating a generic and easily applicable set of techniques and tools for HTH detection. We start by introducing a technique for recovery of characteristics of gates in terms of leakage current, switching power, and delay, which utilizes linear programming to solve a system of equations created using non-destructive measurements of power or delays. This technique is combined with constraint manipulation techniques to detect embedded HTHs. The effectiveness of the approach is demonstrated on a number of standard benchmarks.

Experiences in Hardware Trojan design and implementation

Abstract: We report our experiences in designing and implementing several hardware Trojans within the framework of the Embedded System Challenge competition that was held as part of the Cyber Security Awareness Week (CSAW) at the Polytechnic Institute of New York University in October 2008. Due to the globalization of the Integrated Circuit (IC) manufacturing industry, hardware Trojans constitute an increasingly probable threat to both commercial and military applications. With traditional testing methods falling short in the quest of finding hardware Trojans, several specialized detection methods have surfaced. To facilitate research in this area, a better understanding of what Hardware Trojans would look like and what impact they would incur to an IC is required. To this end, we present eight distinct attack techniques employing Register Transfer Level (RTL) hardware Trojans to compromise the security of an Alpha encryption module implemented on a Digilent BASYS Spartan-3 FPGA board. Our work, which earned second place in the aforementioned competition, demonstrates that current RTL designs are, indeed, quite vulnerable to hardware Trojan attacks.

Security against hardware Trojan through a novel application of design obfuscation

Abstract: Malicious hardware Trojan circuitry inserted in safety-critical applications is a major threat to national security. In this work, we propose a novel application of a key-based obfus-cation technique to achieve security against hardware Trojans. The obfuscation scheme is based on modifying the state transition function of a given circuit by expanding its reachable state space and enabling it to operate in two distinct modes — the normal mode and the obfuscated mode. Such a modification obfuscates the rareness of the internal circuit nodes, thus making it difficult for an adversary to insert hard-to-detect Trojans. It also makes some inserted Trojans benign by making them activate only in the obfuscated mode. The combined effect leads to higher Trojan detectability and higher level of protection against such attack. Simulation results for a set of benchmark circuits show that the scheme is capable of achieving high levels of security at modest design overhead. Categories and Subject Descriptors B.6.1 [Logic Design]: Design Styles-sequential circuits; K.6.5 [Management of Computing and Information Systems]: Security and Protection-physical security General Terms Design, Security

New design strategy for improving hardware Trojan detection and reducing Trojan activation time

Abstract: Hardware Trojans in integrated circuits and systems have become serious concern to fabless semiconductor industry and government agencies in recent years. Most of the previously proposed Trojan detection methods rely on Trojan activation to either observe a faulty output or measure side-channel signals such as transient current or charge. From the authentication stand point, time to trigger a hardware Trojan circuit is a a major concern. This paper analyzes time to (i) generate a transition in functional Trojans and (ii) fully activate them. An efficient dummy flip-flop insertion procedure is proposed to increase Trojan activity. Depending on authentication time and circuit topology, a transition probability threshold is selected so that inserted dummy flip-flops would moderately impact area overhead. The simulation results on s38417 benchmark circuit demonstrate that, with a negligible area overhead, our proposed method can significantly increase Trojan activity and reduce Trojan activation time.

Performance of delay-based Trojan detection techniques under parameter variations

Abstract: Various schemes utilizing path delay information have been proposed to determine the authenticity of a given integrated circuit. However, the performance of these techniques under parameter variations must be evaluated, as delay variations may mask the delay impact of design alterations, such as hardware Trojan horses. This paper examines how path delay characterization performs under extensive delay variations, and results reveal that it remains a powerful tool for detecting design alterations by leveraging statistical techniques.

Cryptographic hardware and embedded systems : CHES 2009 : 11th international workshop, Lausanne, Switzerland, September 6-9, 2009 : proceedings

Abstract: Software Implementations.- Faster and Timing-Attack Resistant AES-GCM.- Accelerating AES with Vector Permute Instructions.- SSE Implementation of Multivariate PKCs on Modern x86 CPUs.- MicroEliece: McEliece for Embedded Devices.- Invited Talk 1.- Physical Unclonable Functions and Secure Processors.- Side Channel Analysis of Secret Key Cryptosystems.- Practical Electromagnetic Template Attack on HMAC.- First-Order Side-Channel Attacks on the Permutation Tables Countermeasure.- Algebraic Side-Channel Attacks on the AES: Why Time also Matters in DPA.- Differential Cluster Analysis.- Side Channel Analysis of Public Key Cryptosystems.- Known-Plaintext-Only Attack on RSA-CRT with Montgomery Multiplication.- A New Side-Channel Attack on RSA Prime Generation.- Side Channel and Fault Analysis Countermeasures.- An Efficient Method for Random Delay Generation in Embedded Software.- Higher-Order Masking and Shuffling for Software Implementations of Block Ciphers.- A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques.- A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions.- Invited Talk 2.- Crypto Engineering: Some History and Some Case Studies.- Pairing-Based Cryptography.- Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers.- Faster -Arithmetic for Cryptographic Pairings on Barreto-Naehrig Curves.- Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves.- New Ciphers and Efficient Implementations.- KATAN and KTANTAN - A Family of Small and Efficient Hardware-Oriented Block Ciphers.- Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security.- Elliptic Curve Scalar Multiplication Combining Yao's Algorithm and Double Bases.- TRNGs and Device Identification.- The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators.- Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs.- CDs Have Fingerprints Too.- Invited Talk 3.- The State-of-the-Art in IC Reverse Engineering.- Hot Topic Session: Hardware Trojans and Trusted ICs.- Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering.- MERO: A Statistical Approach for Hardware Trojan Detection.- Theoretical Aspects.- On Tamper-Resistance from a Theoretical Viewpoint.- Mutual Information Analysis: How, When and Why?.- Fault Analysis.- Fault Attacks on RSA Signatures with Partially Unknown Messages.- Differential Fault Analysis on DES Middle Rounds.

Hardware Trojan by Hot Carrier Injection

Abstract: This paper discusses how hot carrier injection (HCI) can be exploited to create a trojan that will cause hardware failures. The trojan is produced not via additional logic circuitry but by controlled scenarios that maximize and accelerate the HCI effect in transistors. These scenarios range from manipulating the manufacturing process to varying the internal voltage distribution. This new type of trojan is difficult to test due to its gradual hardware degradation mechanism. This paper describes the HCI effect, detection techniques and discusses the possibility for maliciously induced HCI trojans.