Showing papers on "Logarithmic number system published in 1989"

Computational structures for fast implementation of L-path and L-block digital filters

Abstract: One of the major problems in the multi-DSP (digital signal processor) implementation of L-path and L-block digital filters is the hardware complexity-throughput rate tradeoff The author presents computational structures based on the theory of fast algorithms for short linear convolutions, which are suitable for the implementation of these types of digital filters He also compares the performance of the structures with two previously published ones The comparison shows that the schemes proposed here are faster and that the complexity-throughput tradeoffs can easily be controlled by the designer >

Improved addition for the logarithmic number system

Abstract: The logarithmic number system (LNS), which offers a wide dynamic range with an independently choosable signal-to-noise ratio, is discussed. To realize addition, voluminous lookup tables are needed. A method is proposed to reduce the storage requirements of these tables by means of Chebyshev approximation with unequally spaced partition points. >

Algorithm design for a 30-bit integrated logarithmic processor

Abstract: A description is given of the architecture of an integrated processor that is capable of performing addition and subtraction of 30-b numbers with 20 fractional bits in the logarithmic number system. Previous techniques would require 70 Mb of ROM to implement this processor, which is not feasible for a single-chip implementation. The techniques presented here use a factor of 275 less memory. The key to this is the use of a linear approximation of the nonlinear functions stored in the lookup tables. The functions involved are highly nonlinear in some regions, so variable size regions are used for the approximation. The use of linear approximation alone would still require over 565 kb of ROM. Further compression is obtained by using linear approximation with differential coding of each table. The compression is chosen to minimize ROM size and obtains a further reduction of 55%. A total of 260 kb of ROM is required to implement the processor. >

Redundant logarithmic number systems

Abstract: A new number system that offers advantages over conventional floating-point and sign/logarithm number systems is described. Called redundant logarithmic arithmetic, it relies, like conventional logarithmic arithmetic, on table lookups to make the arithmetic unit simpler than an equivalent floating-point unit. The cost of 32-b subtraction in a redundant logarithmic number system is lower than that of previously published logarithmic subtraction methods. Another advantage of a redundant logarithmic number system is that a single arithmetic unit can use the same hardware to add, subtract, or multiply in similar times. >

On-line arithmetic for DSP applications

Abstract: An overview of the principles and features of online arithmetic is given. Applications of online arithmetic in signal processing are discussed, with an emphasis on matrix computations. >

A hybrid floating-point/logarithmic number system digital signal processor

Abstract: The implementation of a novel hybrid floating-point processor is discussed Additions are performed without any need for exponent alignment, and multiplications and divisions are performed in less time than that required for fixed-point additions The processor is based on a combination of the logarithmic number system (LNS) representation with the signal digit (SD) representation The SD number system offers parallelism at the digit level for the implementation of the various operations A novel technique for parallel conversion of SD to sign-magnitude numbers is developed to enhance the overall design The proposed processor compares favorably to previously developed hybrid floating-point processor designs It is at least ten gate delays faster per addition/subtraction and eight gate delays faster per multiplication/division >

Floating point incremental coders in recursive digital filtering

Abstract: By using high-speed differential encoders such as delta (or deltasigma) modulators, simple recursive incremental filters can be built that exhibit low hardware complexity, modularity, and compactness. However, for higher filter orders, the performance of these incremental designs is often unacceptable due to the accumulation of noise from the binary or temary quantizers. By replacing the binary or ternary quantizers with powers-of-two, or floating-point, quantizers, significant performance improvements can be realized with little increase in cost or complexity.

Logarithmic arithmetic circuit device

Abstract: PURPOSE:To reduce the error between an arithmetic value using a logarithm transformation expression and the integer data of the logarithmic arithmetic value by carrying the decimal fractions of the logarithmic arithmetic value or carrying or omitting in accordance with the value of the decimal fraction excluding the time when the first decimal fraction is '0', and operating the integer data of the logarithmic arithmetic value. CONSTITUTION:A first arithmetic circuit executes the logarithmic operation with the approximate expression of the polygonal line approximation for the data inputted. Thereafter, a second arithmetic circuit carries the decimal fractions of the logarithmic arithmetic value outputted from the first arithmetic circuit or carries or omits the decimal fractions in accordance with the value of the decimal fractions of the logarithmic arithmetic value excluding the time when the first decimal fractions of the logarithmic arithmetic value are '0' and the integer data of the logarithmic arithmetic value are operated. Thus, the error between the arithmetic value using the logarithmic converting expression and the integer data of the logarithmic arithmetic value can be reduced.

Implementation of 2-D filters for real-time processing

Abstract: An implementation technique for two-dimensional real-time linear filters with standard hardware elements is introduced. A cost analysis demonstrates that the RAM-based implementation of the elements z/sup -1//sub 1/ causes only a small part of the total cost. Therefore, as in the one-dimensional case, in two-dimensional linear signal processing the implementation cost is primarily dependent on the number of the multipliers and adders. >

Floating point arithmetic and state space digital filters

Abstract: A M r o c f In this paper, the roundoff noise properliea of floating point stale-space digital fllters are examined. To make the analysis tractable, a high level model for the inner product operation is developed. The model establishes a broad connection between coeffleienl sensillvily and roundoff noise. It ia used lo derive an expression for the oulpul roundoff noise behavior of state space fliters when the input is a iero mean wide sense stationary random process. The expressions indicate explicitly the d e pendenee of the roundoff noise on the fllters parameters. the statistics of the input signal, and the addition scheme used in the computation. Some properties and oplimality issues are also considered. It is shown thal when double precision accumulation is used, the optimal flltera are the same m those obtained when fixed point arilbmetic is used. For second order fllters i t is shown that optimal flxed point slruetures are dose to optimal.

A real-time adaptive lattice predictor using a digital signal processor chip

Abstract: A real-time adaptive lattice predictor was implemented using a digital signal processing chip. The implementation comprises input-output units, a central processing and control unit, and supporting software. The performance of the hardware was verified by comparing an input signal and the one-step prediction signal calculated by the predictor. The maximum operating frequency for the four-stage lattice structure was 13.5 kHz. >

Subtractive floating-point division and square root for VLSI DSP

Abstract: This paper describes recent architectural developments in VLSI design for real-time digital signal processing. In particular, floating point division and floating point square root architectures applicable to both adaptive filtering, standard deviation computations, and general purpose processing are discussed. Emphasis here is on the internal architectures of the arithmetic units not on their applications. The research presented in this paper has been proven feasible and reliable from extensive gate-level simulation and fabrication in silicon. >

A hybrid number system multiplier for graphics and complex arithmetic applications

Abstract: A hybrid multiplier design which supports 32-bit floating-point, 24-bit fixed-point and 32-bit logarithmic number systems is described. Except for additions and subtractions, floating-point operations such as multiplication, division, and square root are all performed in the logarithmic number system domain. A modified squaring approach is adopted for fixed-point multiplications with little extra hardware. The performance of this multiplier is shown to be superior to that of conventional binary multipliers for most graphics and digital signal processing applications, and the size of the multiplier is comparable to that of conventional multipliers in terms of silicon area. >

A dual-DSP TMS 320C25 processor system for real time digital correlation

Abstract: A dual-processor system architecture and its application for real-time correlation are explained. This system uses two TMS320C25 digital signal processor (DSP) microprocessors and a dual-port common memory. System design details, theory of digital correlation, and software details are presented. Tables are given in which the performances and features of various DSPs are compared. >

An efficient VLSI implementation of logarithmic signal processors

Abstract: A hybrid logarithmic processor based on the logarithmic number system (LNS) is introduced The LNS exponents of the operands are represented internally using the signed-digit (SD) number system. The LNS exponents, represented traditionally as fixed-point or sign-magnitude numbers, are converted to an SD format and then processed. This allows the parallelism offered by the SD number system at the digital level to be exploited for the implementation of the various operations. In order to reduce the size of the memory tables required for LNS operations like addition to subtraction, a technique for parallel conversion of SD to sign-magnitude numbers is developed. The new processor compares favorably to a previously developed logarithmic processor in terms of computational speed. It also results in a more regular and modal VLSI implementation. >