Journal ArticleDOI
Computational structures for fast implementation of L-path and L-block digital filters
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TLDR
In this paper, the authors present computational structures based on the theory of fast algorithms for short linear convolutions, which are suitable for the implementation of L-path and L-block digital filters.Abstract:
One of the major problems in the multi-DSP (digital signal processor) implementation of L-path and L-block digital filters is the hardware complexity-throughput rate tradeoff The author presents computational structures based on the theory of fast algorithms for short linear convolutions, which are suitable for the implementation of these types of digital filters He also compares the performance of the structures with two previously published ones The comparison shows that the schemes proposed here are faster and that the complexity-throughput tradeoffs can easily be controlled by the designer >read more
Citations
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Journal ArticleDOI
Low-Power and Area-Efficient Carry Select Adder
B. Ramkumar,Harish M. Kittur +1 more
TL;DR: This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA, and develops and compared with the regular SQRT C SLA architecture.
Journal ArticleDOI
Hardware efficient fast parallel FIR filter structures based on iterated short convolution
Chao Cheng,Keshab K. Parhi +1 more
TL;DR: This paper presents an iterated short convolution (ISC) algorithm, based on the mixed radix algorithm and fast convolution algorithm, transposed to obtain a new hardware efficient fast parallel finite-impulse response (FIR) filter structure, which saves a large amount of hardware cost.
Journal ArticleDOI
Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm
Yu-Chi Tsao,Ken Choi +1 more
TL;DR: The proposed parallel FIR structures can lead to significant hardware savings for symmetric convolutions from the existing FFA parallel FIR filter, especially when the length of the filter is large.
Journal ArticleDOI
Low- Cost Parallel FIR Filter Structures With 2-Stage Parallelism
Chao Cheng,Keshab K. Parhi +1 more
TL;DR: The subfilters in the previous parallel FIR structures are replaced by a second stage parallel FIR filter, which can efficiently reduce the number of required multiplications and additions at the expense of delay elements.
Journal ArticleDOI
Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm
Yu-Chi Tsao,Ken Choi +1 more
TL;DR: The proposed parallel FIR structures can lead to significant hardware savings for symmetric convolution in odd length from the existing FFA parallel FIR filter, particularly when the length of the filter is large.
References
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Journal ArticleDOI
Analysis of linear digital networks
R.E. Crochiere,Alan V. Oppenheim +1 more
TL;DR: A framework is presented for the analysis, representation, and evaluation of digital filter structures Based on the notation of linear signal-flow graphs and their equivalent matrix representation, a set of general linear digital network properties are reviewed, including precedence relations computability, Tellegen's theorem, interreciprocity, and network transposition.
Journal ArticleDOI
Fast one-dimensional digital convolution by multidimensional techniques
R. Agarwal,C. Burrus +1 more
TL;DR: The formulation is very general and includes block processing and sectioning as special cases and, when used with various fast algorithms for short length convolutions, results in improved multiplication efficiency.
Journal ArticleDOI
Block-shift invariance and block implementation of discrete-time filters
C. Barnes,S. Shinnaka +1 more
TL;DR: In this article, a general class of linear, time-invariant multivariable systems that can be used in block implementations of discrete-time filters are described, including an explicit expression for the matrix transfer function of the block processor in terms of the single-input, single-output filter transfer function.
Journal ArticleDOI
Design of high-speed digital filters suitable for multi-DSP implementation
TL;DR: A multi-DSP hardware system is outlined which is specifically designed for implementing the multipath structures discussed here, which are specifically suitable for implementation using a number of Digital Signal Processors (DSP).
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