Showing papers on "Logarithmic number system published in 1998"
TL;DR: Two co-transformations that accomplish this goal are introduced, an approximation based on real analysis of the subtraction logarithm and a simple algebra that applies for both real and complex values and that works for both addition and subtraction.
Abstract: The real logarithmic number system, which represents a value with a sign bit and a quantized logarithm, can be generalized to create the complex logarithmic number system, which replaces the sign bit with a quantized angle in a log/polar coordinate system. Although multiplication and related operations are easy in both real and complex systems, addition and subtraction are hard, especially when interpolation is used to implement the system. Both real and complex logarithmic arithmetic benefit from the use of co-transformation, which converts an addition or subtraction from a region where interpolation is expensive to a region where it is easier. Two co-transformations that accomplish this goal are introduced. The first is an approximation based on real analysis of the subtraction logarithm. The second is based on simple algebra that applies for both real and complex values and that works for both addition and subtraction.
56 citations
10 Aug 1998
TL;DR: This paper investigates the low power implementation issues of the Soft-Output Viterbi algorithm (SOVA), a building block for turbo codes, and develops an architecture that completes those computations with reduced power consumption.
Abstract: An important technique for reducing pow er consumption in VLSI systems is strength reduction, the substitution of a less-costly operation such as a shift, for a more-costly operation such a multiplication. Using a logarithmic number represen tation provides sev eral opportunities for strength reductions; in particular, m ultiplicationis performed as the fixed-point addition of logarithms, and extracting a square root is implemented via a shift. These reductions occur transparently at the hardware level; consequently relativ ely little algorithmic modification is required, and they are readily applicable to adaptive filtering. For performing Givens rotations in the QR decomposition recursiv e least squares adaptive filter, logarithmic arithmetic is shown to compare favorably to other strength reduction techniques, such as CORDIC arithmetic, in terms of switched capacitance and numerical accuracy.
50 citations
10 Aug 1998
TL;DR: For performing Givens rotations in the QR decomposition recursive least squares adaptive filter, logarithmic arithmetic is shown to compare favorably to other strength reduction techniques, such as CORDIC arithmetic, in terms of switched capacitance and numerical accuracy.
Abstract: An important technique for reducing pow er consumption in VLSI systems is strength reduction, the substitution of a less-costly operation such as a shift, for a more-costly operation such a multiplication. Using a logarithmic number represen tation provides sev eral opportunities for strength reductions; in particular, m ultiplicationis performed as the fixed-point addition of logarithms, and extracting a square root is implemented via a shift. These reductions occur transparently at the hardware level; consequently relativ ely little algorithmic modification is required, and they are readily applicable to adaptive filtering. For performing Givens rotations in the QR decomposition recursiv e least squares adaptive filter, logarithmic arithmetic is shown to compare favorably to other strength reduction techniques, such as CORDIC arithmetic, in terms of switched capacitance and numerical accuracy.
24 citations
TL;DR: A new class of number systems is presented that constitute a family of various compromises between floating-point and logarithmic number systems, that allows trade between the speed of the arithmetic operations and the size of the required tables.
Abstract: We present a new class of number systems, called Semi-Logarithmic Number Systems, that constitute a family of various compromises between floating-point and logarithmic number systems. This allows trade between the speed of the arithmetic operations and the size of the required tables. We give arithmetic algorithms (addition/subtraction, multiplication, division) for the Semi-Logarithmic Number Systems, and we compare these number systems to the classical floating-point or logarithmic number systems.
19 citations
TL;DR: In this paper, the effects of roundoff noise in finite-impulse response (FIR) digital filters implemented using a logarithmic number system are examined, and expressions for the ratio of output variance with roundoff errors to output variance without roundoff error are derived.
Abstract: The principal factors influencing the design and implementation of most real-time digital filters are accuracy, speed, and ease of implementation. In this work, the effects of roundoff noise in finite-impulse response (FIR) digital filters implemented using a logarithmic number system are examined. Expressions for the ratio of output variance with roundoff errors to output variance without roundoff errors are derived. The noise performance of logarithmic FIR filters is compared to that of floating-point FIR filters. Simulation results are provided which confirm the theoretical results of error analysis.
13 citations
12 May 1998
TL;DR: This work has demonstrated that trading precision for dynamic range through the use of floating point and logarithmic number system representations can potentially provide power savings for subband speech coding applications.
Abstract: In low power VLSI design, fixed point number representations are standard. For some signal processing applications, however, achieving sufficient dynamic range with fixed point may lead to computations utilizing more precision than necessary. In such cases, trading precision for dynamic range through the use of floating point and logarithmic number system representations can potentially provide power savings. This is demonstrated for a subband speech coding application using architectural-level capacitance modeling.
9 citations
07 Sep 1998
TL;DR: The organization and the VLSI implementation of a Very Long Instruction Weld (VLIW) Digital Signal Processor are discussed in this paper, which has the ability to issue concurrently up to thirty elementary instructions, the two LNS execution units including division, and the dynamic range offered by the 33-bit data word.
Abstract: The organization and the VLSI implementation of a Very Long Instruction Weld (VLIW) Digital Signal Processor are discussed in this paper. The processor operates in the Logarithmic Number System (LNS) and it features two LNS execution units. Each execution unit contains a single-clock multiply/divide unit and a pipelined adder/subtracter of dynamic range equivalent to the single-precision IEEE 754 standard requirements. The architecture is optimized for the execution of FIR and IIR filters, as well as any sum-of-products based digital signal processing algorithm. The full exploitation of the independent resources is facilitated by porting the complexity of resolving the dependencies among the instructions from special control hardware to the organization of the application software, an off-line task. The main characteristics of the introduced processor include the ability to issue concurrently up to thirty elementary instructions, the two LNS execution units including division, and the dynamic range offered by the 33-bit data word. The chip has been designed and simulated in a commercial 0.7-/spl mu/m CMOS technology.
6 citations
05 Oct 1998
TL;DR: The proposed method makes large word-length LNS arithmetic possible and is computed that the size of the lookup tables used in a 33-bit LNS unit is about 0.543 Mbits, which is very small.
Abstract: Logarithmic number system (LNS) has the advantages of regular data flow high speed, and high precision. However, the development of LNS arithmetic is hindered by the large size of the lookup tables used in LNS addition/subtraction, since the size is exponentially proportional to the word length of the operands. To overcome this large-table problem, LNS addition/subtraction is proposed to be computed in a pipelined manner. The computation includes an exponential stage and a logarithmic stage. The exponential stage is implemented by using digit-parallel additive normalization and the logarithmic stage is implemented by using digit on-line multiplicative normalization. It has been computed that the size of the lookup tables used in a 33-bit LNS unit is about 0.543 Mbits, which is very small. The hardware cost of the other circuits in this LNS unit is only linearly proportional to the word length of the operands. We conclude that the proposed method makes large word-length LNS arithmetic possible.
3 citations