Showing papers on "Logarithmic number system published in 2003"

CMOS VLSI implementation of a low-power logarithmic converter

Abstract: We present a unique 32-bit binary-to-binary logarithm converter including its CMOS VLSI implementation. The converter is implemented using combinational logic only and it calculates a logarithm approximation in a single clock cycle. Unlike other complex logarithm correcting algorithms, three unique algorithms are developed and implemented with low-power and fast circuits that reduce the maximum percent errors that result from binary-to-binary logarithm conversion to 0.9299 percent, 0.4314 percent, and 0.1538 percent. Fast 4, 16, and 32-bit leading-one detector circuits are designed to obtain the leading-one position of an input binary word. A 32-word/spl times/5-bit MOS ROM is used to provide 5-bit integers based on the corresponding leading-one position. Both converter area and speed have been considered in the design approach, resulting in the use of a very efficient 32-bit logarithmic shifter in the 32-bit logarithmic converter. The converter is implemented using 0.6/spl mu/m CMOS technology, and it requires 1,600/spl lambda//spl times/2,800/spl lambda/ of chip area. Simulations of the CMOS design for the 32-bit logarithmic converter, operating at V/sub DD/ equal to 5 volts, run at 55 MHz, and the converter consumes 20 milliwatts.

An automated floating-point to fixed-point conversion methodology

Abstract: We propose a floating-point to fixed-point conversion (FFC) methodology for digital VLSI signal processing systems. The past techniques used to facilitate FFC are first reviewed, followed by a description based on a statistical approach and global optimization which allows a high degree of automation.

A VHDL library of LNS operators

Abstract: Logarithmic number system (LNS) have been shown to be a competitive replacement of floating-point (FP) arithmetic, for precisions up to 32 bits. This paper presents a library of LNS operators aimed at smaller precisions typical of DSP applications. The novelty of our approach is the use of multipartite table compression in the addition and subtraction operators. The paper compares this approach to other published implementations, and to similar FP operators. The operators have been developed and tested on FPGAs, but they are written in fairly standard VHDL. They are available for download from www.ens-lyon.fr/LIP/Arenaire.

Loading the bases: a new number representation with applications

Abstract: A number system has recently been introduced that uses two orthogonal bases (Double-base Number System-DBNS). In its direct form the system provides a very sparse two-dimensional number representation which appears, initially, to be a curiosity. After some research by our group, however, the number system has proved to have some interesting and potentially far-reaching applications. The number system has been extended to more than 2 bases and a logarithmic version, which we refer to as the Multi-dimensional Logarithmic Number System (MDLNS), has also proved useful for implementing digital filters. An important property of the MDLNS, that the computational complexity associated with each base reduces both as the number of bases and as the number of digits (or logarithmic components) increase, gives rise to some simple implementation procedures. In this article we will explore some of the theory of the linear and logarithmic systems associated with this new representation, and provide examples of applications in cryptography and digital filter implementation.

A dual-path logarithmic number system addition/subtraction scheme for FPGA

Abstract: A new architecture for calculating the addition/subtraction function required in a logarithmic number system (LNS) is presented. A substantial logic saving over previous works is illustrated along with similarities with the dual-path floating-point addition method. The new architecture constrains the lookups to be of fractional width and uses shifting to achieve this. Instead of calculating the function log 2 (1±2 M-K ) in two lookups the function arithmetic is performed (i.e. the two functions 2 M-K and log 2 ( ), plus a correction function) as this allows logic sharing that maps well to FPGA. Better-than-floating-point (BTFP) accuracy is used to enable a future comparison with floating-point.

A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA

Abstract: A new architecture for calculating the addition/subtraction function required in a logarithmic number system (LNS) is presented. A substantial logic saving over previous works is illustrated along with similarities with the dual-path floating-point addition method. The new architecture constrains the lookups to be of fractional width and uses shifting to achieve this. Instead of calculating the function \(\log_2(1\pm2^{M-K})\) in two lookups the function arithmetic is performed (i.e. the two functions 2M − K and log2( ), plus a correction function) as this allows logic sharing that maps well to FPGA. Better-than-floating-point (BTFP) accuracy is used to enable a future comparison with floating-point.

Feasibility of fixed-point transversal adaptive filters in FPGA devices with embedded DSP blocks

Abstract: Transversal adaptive filters for digital signal processing have traditionally been implemented into DSP processors due to their ability to perform fast floating-point arithmetic. However, with its growing die size as well as incorporating the embedded DSP block, the FPGA devices have become a serious contender in the signal processing market. Although it is not yet feasible to use floating-point arithmetic in modern FPGAs, it is sufficient to use fixed-point arithmetic and still achieve tap-weight convergence for adaptive filters. This paper examines the feasibility of implementing an adaptive algorithm, namely the LMS algorithm, based on fixed-point arithmetic, using the Altera Stratix device.

Error Analysis of the Kmetz/Maenner Algorithm

Abstract: Use of low-precision logarithms can minimize power consumption and increase the speed of multiply-intensive signal-processing systems, such as FIR filters. Although straight table lookup is the mos...

The interval logarithmic number system

Abstract: We introduce the interval logarithmic number system (ILNS), in which the logarithmic number system (LNS) is used as the underlying number system for interval arithmetic. The basic operations in ILNS are introduced and an efficient method for performing ILNS addition and subtraction is presented. We compare ILNS to interval floating point (IFP) for a few sample applications. For applications like the N-body problem, which have a large percentage of multiplies, divides and square roots, ILNS provides much narrower intervals than IFP. In other applications, like the fast Fourier transform, where addition and subtraction dominate, ILNS and IFP produce intervals having similar widths. Based on our analysis, ILNS is an attractive alternative to IFP for application that can tolerate low to moderate precisions.

A VLIW architecture for logarithmic arithmetic

Abstract: The Logarithmic Number System (LNS) is an alternative to IEEE-754 standard floating-point arithmetic. LNS multiply, divide and square root are easier than IEEE-754 and naturally belong to the same class of one-cycle-latency instructions like integer addition, subtraction and shifting. LNS addition is harder, requiring several cycles if the integer add determines the clock. Unlike prior LNS Instruction Set Architectures (ISAs), the proposed ISA uses a separate pipelined unit specialized for LNS addition that operates in parallel to a faster LNS-multiply-divide/integer-add unit. Their latencies are different: the former uses four to six cycles; the latter uses only one. The proposed Very Long Instruction Word (VLIW) architecture includes novel LNS increment-multiply and input-conversion instructions that improve performance at very low cost. The ISA overloads a novel comparison flag: LNS-less-than for divide and integer-less-than for subtract. Features of other ISAs are omitted here due to hidden costs of feeding extra operands to the ALUs. The proposed ISA offers multiplication bandwidth equal to (not higher than) that of addition. Also, omitting a multiply-accumulate instruction does not degrade LNS performance at all.

A parallel look-up logarithmic number system addition/subtraction scheme for FPGA

Abstract: This paper presents results from the design of an LNS addition/subtraction function targeted for implementation on FPGA. A parallel look-up scheme is used to reduce the critical path of the function approximation to a single second order polynomial approximation while maintaining an acceptable amount of ROM to store the coefficients needed to calculate the logarithmic addition/subtraction function. The addition/subtraction function is designed to have better-than-floating-point accuracy, which enables a fair future comparison with floating-point. Area and delay reductions are achieved in comparison with previous designs.

Fast Fourier Transforms Using the Complex Logarithmic Number System

Abstract: The complex-logarithmic number system (CLNS), which represents each complex point in log/polar coordinates, may be practical to implement the Fast Fourier Transform (FFT). The roots of unity needed by the FFT have exact representations in CLNS and do not require a ROM. We present an error analysis and simulation results for a radix-two FFT that compares a rectangular fixed-point representation of complex numbers to CLNS. We observe that CLNS saves 9–12 bits in word-size for 256–1024 point FFTs compared to the fixed-point number system while producing comparable accuracy. The consequence of the word-size advantage is that the number of full adders required for CLNS is significantly smaller than for an equivalent fixed-point implementation. The major cost of CLNS is the memory, which unlike conventional LNS, is addressed by both real and imaginary parts. Table-reduction techniques can mitigate this. The simplicity of the CLNS approach requires significantly fewer full adders, which pays for some or all of the extra memory. In applications needing the magnitude of the complex parts, such as a power spectrum, the CLNS approach can actually require less memory than the conventional approach.

Iterative methods for logarithmic subtraction

Abstract: The logarithmic number system (LNS) offers much better performance (in terms of power, speed and area) than floating point for multiplication, division, powers and roots. Moderate-precision addition (of like signs) in LNS generally can be done with table lookup followed by interpolation, whose implementation can be as, or more, efficient than the equivalent precision floating-point adder. The problem with LNS is the size of the table needed for subtraction. We consider iterative methods for logarithmic subtraction. The basis for the novel methods proposed here is that the subtraction logarithm is the inverse of the addition logarithm. Although the mathematics for this kind of logarithmic subtraction were first described during the time of Gauss, no modern designer has implemented an algorithm, like the one proposed here, which performs a binary search followed by an inverse interpolation. Additionally, we propose a novel initialization step for the binary search, which doubles the speed of the algorithm compared to a name, implementation. Combining the proposed method with other iterative methods may reduce the average execution time further. Synthesis results indicate the proposed methods are feasible for FPGA implementation.

Logarithmic arithmetic for real data types and support for Matlab/Simulink based rapid-FPGA-prototyping

Abstract: The paper is focused on the rapid prototyping for FPGA using the high-level environment of MATLAB/Simulink. An approach using the Xilinx system generator (XSG) is reviewed on an example of the high-speed logarithmic arithmetic (HSLA) unit. An alternative approach using the combination of the real time workshop (RTW) with the Handle-C compiler for automatized generation of the HDL code is presented. Finally, the possibilities to extend this solution in order to support the run-time reconfigurations are outlined.

Logarithmic number system and floating-point implementations of a well-conditioned RLS estimation algorithm on FPGA

Abstract: This paper presents the results from the implementation of a recursive least squares estimation algorithm on FPGA and compares the implementation using two types of arithmetic. The estimation uses an orthogonal set of discrete Chebyshev polynomials to overcome the ill-conditioning problem that is exhibited by the classical least mean squared linear regression algorithm using the Taylor expansion. A recursive form of the algorithm is implemented at varying precision word lengths on FPGA using a recently developed set of logarithmic number system macros and a set of parametrised IEEE-754 compliant floating-point cores. Speed and area metrics are presented.

Performance of the European logarithmic microprocessor.

Abstract: We have developed a new microprocessor. In contrast to existing devices, which perform real arithmetic using the floating-point system, the European Logarithmic Microprocessor uses the logarithmic number system for this purpose. This paper describes the ELM device, and compares its architecture with that of a conventional floating-point digital signal processor. We then illustrate the operation of both devices using an example from a class of recursive-least-squares algorithms. The results suggest that logarithmic arithmetic may be of particular benefit in applications with less regular processing patterns, e.g. in scalar or short vector code or triangular matrix processing, or where there is a preponderance of multiplications or significant use of division or square-root operations. These criteria appear to point to the more advanced digital adaptive filtering algorithms, and also to graphics applications. Results indicate that the logarithmic number system also offers an improvement in accuracy of around one bit.

Converting integer to floating point number

Abstract: Conversion of integer to floating-point number is a frequent operation in high performance DSP processor, and direct conversion is time consuming. An improved method of converting integer to floating point number is presented in this article, in which leading zero is preserved until rounding and complementation are preformed, and normalization is done after rounding, rounding and complementation are combined, so that hardware cost is reduced and complexity of conversion is decreased. The method is used in the design of a DSP processor, and the design is synthesized, verified and implemented with FPGA.

Asymmetric and compressed logarithmic number systems for multimedia coprocessor (invited paper)

Abstract: The logarithmic number system (LNS) represents a real number with its sign and the logarithm of its absolute value. Inexpensive logarithmic arithmetic has shorter word length than fixed point. Conventional LNS is symmetrical: every reciprocal is representable. This paper proposes asymmetrical LNS (one sixteenth to 2048) with acceptable visual quality for MPEG decoding that saves one bit compared to conventional LNS. Novel compression saves another bit with only slight image degradation and allows 8 by 8 matrices to fit in 64 (not 128) bytes. The proposed LNS inverse discrete cosine transform (IDCT) coprocessor is compatible with conventional byte-sized packed-arithmetic SIMD architectures.

Optimization of 16 bit fix-point multiplication in fast DCT implemented on TMS320C2000 DSP

Abstract: Multiplication in the implementation of JPEG algorithm on fix-point 16-bit digital signal processing does not only have an influence on the calculation time of compression performing but also on the quality of the decompressed images. Its implementation therefore, is usually balanced between accuracy and performing speed. One possible optimization when considering the TSM320C2000 digital signal processor family, is presented.

A 24-bit floating-point audio DSP controller supporting fast exponentiation

Abstract: This paper describes a 24-bit floating-point DSP controller developed for audio applications. For easy system design, a floating-point DSP and interface blocks including USB, I/sup 2/S, and UART are integrated onto a single chip. Based on the floating-point arithmetic optimized for audio processing algorithms, a fast, single-cycle floating-point unit is designed to achieve high performance. In addition, a special unit to calculate exponential function is proposed. The exponentiation unit uses three instructions to compute x/sup y/ without losing audio quality.