Showing papers on "Master clock published in 1994"

A theory of clock synchronization (extended abstract)

Abstract: EXTENDED ABSTRACT Boaz Patt-Shamir* Sergio Raj sbaumt Laboratory for Computer Science Massachusetts Institute of Technology

Asynchronous self-tuning clock domains and method for transferring data among domains

Abstract: One or more domains are independently clocked with separate clocks. Each clock is an asynchronous stop/start clock implementing a self-tuning clocking methodology. Domain circuit speed is monitored and the clock adjusted to tune the domain to run at near maximum speed. Inter-domain data transfers are performed by a four-way handshaking method. In effect the clock period of the respective clocks during the data transfer becomes the slower period of the two domains' clock periods. An inter-domain arbiter is implemented at each domain for deciding which domain's request is to be granted during an immediate clock period. Data input to a domain is tracked to determine when data is present. When no data is present, the domain's clock is stopped.

Timing circuit for video display having a spatial light modulator

Abstract: A method and apparatus for synchronizing display timing in a digital television system with a pixel addressable display having a color wheel is disclosed. The display timing circuit 22 includes phase comparator 40, for comparing the phase of a wheel index signal generated by a color wheel 20 with the phase of a frame synchronization signal indicating that a complete frame is ready to be displayed. Display timing circuit 22 further comprises a color wheel synchronization generator 42 which generates a color wheel synchronization signal in response to a phase difference value produced by phase comparator 40. The color wheel synchronization signal is used to increase, decrease, or maintain the speed of color wheel 20 to achieve a known phase relationship between the frame synchronization signal and the wheel index signal. Display timing circuit 22 further comprises a clock generator applicable to generate a display master clock signal having a known frequency relation to the wheel index signal.

Data transfer system and method including tuning of a sampling clock used for latching data

Abstract: The timing of digital signal sampling at a receiver is continuously adjusted relative to a master clock used to initiate sending, by controlling a phase difference between the receiver sampling clock and the master clock in accordance with feedback of an error signal determined by detecting deviation of sampling clock timing from desired reference timing during both start-up operation and normal operation. Propagation delay scattering in the individual devices is compensated for by setting the sampling clock at a desired reference timing at start-up. Propagation delay scattering caused by fluctuation during device operation is compensated for by detecting the deviation of the sampling clock timing from reference timing based on received digital signals during normal operation and then continuously correcting the sampling clock timing on the basis of the detection result.

Data transferring circuit which aligns clock and data

Abstract: A network (10) includes a broadband customer service module (B-CSM) (20). The B-CSM (20) includes a plurality of feeder interface cards (FICs) (36) and optical line cards (OLCS) (38) which are coupled together through a midplane assembly (34) so that each FIC (36) couples to all OLCs (38) and each OLC (38) couples to all FICs (36) through junctor groups (68). The B-CSM (20) interfaces many OC-12 SONET feeders to many OC-12 SONET lines. Within the B-CSM (20) circuit switching is performed electrically at an STS-1 rate. A reference clock which oscillates at a frequency lower than the data rate is routed with payload data so that it receives delays similar to those imposed on the payload data due to processing. At second stage switching fabrics (50) where data need to be extracted from signals flowing within the B-CSM (20), a clock regeneration circuit (32) generates a master clock signal oscillating at twice the data rate and phase synchronized to a delayed reference clock. A geometric compensation scheme corrects for timing skew which occurs when clocks and data are distributed to points or small areas from widely dispersed locations, and when clocks and data are distributed from points or small areas to widely dispersed locations.

Method of ensuring that each node of a private telecommunication network is synchronized to the best available clock at all times

Abstract: In a method of synchronizing nodes of a private telecommunication network to the best available clock at all times, each node of the network is normally synchronized by externally originated clock signals which reach it via a point-to-point digital transmission link input. Two node inputs are preselected as main and backup master clock inputs and each node is selectively preselected as a potential supplier of clock signals to each of the nodes to which it is connected by one of its master clock inputs, the nodes of the private network interconnected in this way determining a synchronization tree. In the event of loss of clock signals an exchange of information is instigated between adjacent nodes to reconfigure the synchronization tree that these nodes constitute so that each of them is synchronized to the best available clock.

Optical disk apparatus for recording/erasing information in the M-CAV format by using gain switching to increase the speed of the master clock

Abstract: An apparatus for recording data on an M-CAV-formatted optical disk. The disk has a plurality of substantially concentric tracks grouped into a plurality of zones arranged in a radial direction of the disk. Each of the zones is divided into the same number of sectors, each used as a unit area, and has a different assigned frequency at which to read read data from the sectors. Header information is recorded in the start region of each sector and identifies the sector. Provided next to the start region is a data field in which data is to be recorded. The apparatus is designed to record data in the data field by using a master clock signal having a specific frequency assigned to the zone including that data field. The apparatus has a master clock setting circuit for setting the frequency assigned to any zone to which the zone will be switched from the zone in which data is being recorded. When the zone is switched to that zone, the gain of the master clock setting circuit is increased temporarily, thereby switching the frequency of the master clock signal within a short time.

Asynchronous clock switching between first and second clocks by extending phase of current clock and switching after a predetermined time and appropriated transitions

Abstract: A microprocessor having two on-board clock generators. The faster clock generator controls the microprocessor during normal, synchronous mode. The slower clock generator controls the microprocessor when the bus must be accessed, or during "snoop" mode which is invoked when another entry signals intent to use the bus. A microprocessor having two on-board clock generators. The faster clock generator controls the microprocessor during normal, synchronous mode. The slower clock generator controls the microprocessor when the bus must be accessed, or during "snoop" mode which is invoked when another entity signals intent to use the bus.

Optical 3D measuring apparatus used for measuring chamber volume of a cylinder head and chamber volume correcting method for a cylinder head of an engine

Abstract: A 3D volume measuring apparatus using an optical measuring technique performs an accurate measurement by using a common master clock signal to move a slit beam and to perform a measuring operation using the slit beam. An optical sensor has a slit beam source which projects the slit beam onto a surface of an object. A video camera receives an image of the optical cutting line. A master clock pulse generating unit is provided for generating master clock pulses. The slit beam is scanned on the object in synchronization with the master clock pulses. Information of the image of the optical cutting line is obtained in synchronization with the master clock pulses, so that the contour of the vertical section corresponding to the optical cutting line is obtained. A chamber volume correcting method using the 3D volume measuring apparatus is provided in which method an exact cutting depth for a cylinder head can be calculated so that a chamber of the cylinder head has an exact target volume. The cutting depth is determined in accordance with the measured volume of the chamber before a finish machining is performed.

Two-wire electronic module for remote digital clocks

Abstract: An electronic system is used with one or more digital clocks. The electronic system comprises a two-wire module, attached to the digital clock, for allowing each digital clock to be run and reset to the correct time. A master clock controls a DC supply voltage applied to the two-wire module. The DC supply voltage keeps the digital clock in synchronization with the master clock. Interrupting the DC supply voltage and subsequently reapplying the DC supply voltage causes the two-wire module to set the digital clock to a predetermined time. Reversing polarity of the DC supply voltage for a calibrated time period electronically activates the two-wire module to reset the digital clock to the correct time.

Programmable timing unit for generating multiple coherent timing signals

Abstract: A programmable timing unit having a number of event markers circuits that receive a master clock signal and generate an output when a predetermined time occurs. Optionally, the event marker circuit can add an interpolated delay time to provide greater resolution than the master clock circuit. The output is programmably coupled to any of a number of function circuits. Each function circuit has a trigger input for receiving the event signal and output for providing the delayed output function.

Electronically tuneable computer clocking system and method of electronically tuning distribution lines of a computer clocking system

Abstract: A resonant clocking system is described which utilizes a feedback clock signal from the master clock node on a clocked chip and wherein the feedback clock signal is detected with a phase detector to determine the relevant phasing of the transmitted and the feedback received clock signals. An electronically controllable delay element is disposed within the transmission path of the clock signal on both the transmission leg and the return leg so that equal amounts of delay time may be added to the flight time in each direction. The delay may be electronically controlled to bring a "Transmitted Clock" pulse and a "Received Clock" pulse into phase. By insuring that the delay time for the entire transmission of the circuit by a particular clock pulse is an even number of cycle times, the master clock node on the clocked chip also may be controlled to be in phase with the "Transmitted Clock" pulse signal. This may be accomplished by initially calibrating the system at one-half of normal operating frequency and bringing "Transmitted Clock" pulse and "Received Clock" or feedback pulse into phase. Thereafter, upon returning to normal operating frequency, there always will be an even integral number of cycles of time delay between the transmission of the clock pulse by the oscillator and the receipt of that identical clock pulse by the phase detector; additionally, the pulse at the master clock mode will be in phase.

Data transmission system having dedicated clock channel

Abstract: The clock demodulator 25 continually demodulates the clock signal of the control CPU 7 transmitted from the clock modulator 10 of the center S. The terminal control CPU 23 performs processes such as transmission and reception of data with the demodulated clock signal as a reference clock. The time required to synchronize the clocks of the CPUs 7 and 23 is eliminated. Transmission and reception of data is executed quickly as soon as right of transmission is transferred to a terminal.

On chip clock skew control method and apparatus

Abstract: ON CHIP CLOCK SKEW CONTROL METHOD AND APPARATUS ABSTRACT OF THE DISCLOSURE A master clock signal, used to operate the clock devices (e.g., flip flops) formed on an integrated circuit chip, includes first and second clock paths. The first clock path is a linear trunk having laterally extending tributaries. The clock trunk is driven, through buffer circuits, at both ends with the master clock, and the internal devices coupled to the tributaries to receive the clock signal. The second path comprises a closed loop formed proximate the periphery of the integrated circuit chip. Clock buffer circuitry receives the master clock signal and apply that master clock signal to two points on the closed loop path. The closed loop path is used to communicate the master clock to only the input/output devices, i.e., those that receive data and/or informational signals from an external source, or those communicate such signals to a destination external to the integrated circuit.

I.S. Machine

Abstract: An I.S. machine system has a number of mechanisms which are driven by an inverter drive and a number of machine and section mechanisms which are driven by profiled motion actuators which are controlled by repetitive sequencers associated with each actuator. These repetitive sequencers are synchronized by taking the reference signal from a master clock which supplies the reference signal to the inverters and converts it to a once/cut sync signal for the machine mechanisms operated by profiled motion actuators and to a once/cycle sync signal for the section mechanisms and controllers.

Composite video sub-pixel timing adjustments using digital resampling

Abstract: Composite video timing adjustments using digital resampling provides precise sub-pixel timing relative to a timing reference with a single video master clock. A digital resampler interpolates an input digital composite video signal as a function of a phase offset input which defines a fractional clock period of the video master clock derived from the timing reference. The sub-pixel offset digital composite video signal also may be adjusted by integer multiples of the video master clock period using a FIFO memory. The final timing adjusted digital composite video signal then is input to an analog reconstruction circuit to provide an output analog composite video signal that is precisely timed to the timing reference.

Digital phase locked loop

Abstract: A digital oscillator (11) is synchronized to a master clock by comparing the master clock to an output of the digital oscillator (11) by providing both to a first register (15) which enables a counter (16) The counter (16) increments while enabled until cleared The output of the counter (16) is then compared with a stored signal Depending upon the match with the stored signal, the output of the digital oscillator (11) is either slowed, advanced or maintained The output from the digital oscillator (11) is then fed back to an input of the digital phase locked loop (10)

Method and apparatus for synchronising clocks being connected to a network system

Abstract: Many devices (in particular white goods or brown goods) in a household may contain a clock. Some systems allow to connect all these devices and the related clocks to a common bus or network. The commands for controlling the clocks are in general limited to reading or writing a given time or to broadcasting the time of a given clock to one dedicated device or to the entire system or to a part of the system. In such known systems it is not specified in which manner a clock should react if it receives the time broadcast by another clock. It is possible to initialise all clocks to a given time but due to tolerances in the different clocks, so achieved synchronisation will not be maintained. Regular broadcasting by a special device 'master clock' has the disadvantage of introducing one device with different capabilities. In case there are several master clocks, conflicts may occur and the advantages of a high precision clock will fade away if a lower precision master clock overrides it. One solution is, that only the clock with the highest precision broadcasts its time to the system, but whenever it fails the next lower precision clock takes over the broadcasting automatically. The broadcast periods are defined as factorial periods of a preselected time period. Another possibility is, that all devices will broadcast the time with an equal period but with a different phase and only if no broadcast was received in the preceding time period.

Self-stabilizing wait-free clock synchronization

Abstract: A protocol which can tolerate any number of processors failing by ceasing operation for unbounded time and resuming operation (with or) without knowing that they were faulty is called wait-free; if it also works correctly even when the starting state of the system is arbitrary, it is called wait-free, self-stabilizing. This work is on the problem of wait-free, self-stabilizing clock synchronization of n processors in "in-phase" multiprocessor systems and presents a protocol that achieves quadratic synchronization time, by "re-parameterizing" and improving the best previously known solution, which had cubic synchronization time. Both the protocol and its analysis are intuitive and easy to understand.

Clock switching circuit

Abstract: PURPOSE: To prevent the occurrence of streaks at the time or switching in the case of using a master clock and a slave clock by switching. CONSTITUTION: At the time of normalcy, an output (d) of a D type flip flop DFF 3 is set to the high level to select a driver 4A, and a master clock (a) from a master clock source 1A is used. If abnormality occurs in the master clock (a), this state is detected by a clock monitor circuit 2, and a signal (b) in the high level is given to the D terminal of the DFF to set the output (d) of the DFF 3 to the low level synchronously with the rise of a slave clock (c) from a slave clock source 1B, and a driver 4B is selected; and thus, the driver is switched synchronously with the slave clock (c) to prevent the occurrence of streaks. COPYRIGHT: (C)1995,JPO

Digital signal processor

Abstract: PURPOSE: To reduce the power consumption of the whole digital radio terminal by outputting a master clock request signal only in the processing operation of a DSP. CONSTITUTION: The clock control part of the digital signal processor consists of a clock generation part 1, a sleep setting part 2, a sleep resetting control part 3, and a master clock request part 4, and a sleep is set by software and an external sleep request to outputs the master clock request signal 9 of 'LOW'. At an interruption request 11, on the other hand, the master clock request signal 9 of 'H' is outputted. Only when the request signal 9 is 'H', the master clock is supplied to the DSP outside the DSP, so that the power consumption of the radio terminal can easily be made low. COPYRIGHT: (C)1995,JPO

Didital pll device

Abstract: PURPOSE:To obtain a phase error signal of high accuracy in a time unit smaller than the cycle of a master clock. CONSTITUTION:An edge detection signal ED obtained by detecting the edge of an input signal in a master clock unit is suppied to a shift register 51. The output of the register 51 is sent to a latch circuit 53 via a window circuit 52, and a decoder 54 detects the presence or absence of the input signal edge and also the edge position. An edge position signal EP showing the edge position in a master clock is supplied to a shift register 56. The output of the register 56 is selected by the signal ED and fetched by the circuit 53. Then a subtractor 55 subtracts the value equivalent to the edge position of the phase difference 0 (reference phase) from the output obtained by synthesizing the selected output with the output of the decoder 54. Thus the phase error of the input edge is obtained.

Audio signal reproduction device

Abstract: PURPOSE:To prevent production of reflected noise due to a video signal horizon tal synchronizing frequency (fH) or a harmonic wave component of the fH by setting a frequency of a clock signal fed to an A/D converter to the fre quency fH or an integral multiple of the fH. CONSTITUTION:A master clock of a memory controller 7 is generated from an oscillation circuit employing a ceramic oscillator 13, and an AD clock fed to an A/D converter 6 and a DA clock fed to a D/A converter 10 is generated by frequency-dividing the master clock in the memory controller 7. In the case of, e.g. a still picture, an audio signal for usual reproduction in 3sec before a still picture button is depressed is fetched normally in a memory 8 and the audio signal at a usual speed is ADD-converted, then the frequency of the AD clock and the DA clock is set the same. On the other hand, in the case of the double speed mode, the audio signal of double speed is restored to the usual speed and the S/N of the reproduction signal similarly to the still picture mode is secured, the AD clock frequency is set twice the DA clock frequency.

Circuit driving multi-shift register

Abstract: The circuit processes shift pulses in the block unit and drives multi shift register disabling non operating block The circuit comprises as follows; frequency demultiplier (10) is the circuit demultiplying shift clock which divides the master clock to output, a main shift register (20) inputting the signal to be set by horizontal synchronous signal to shift the input signal and input the shifted output signal on synchronizing the input pulse of the mainshift register and input master clock for another input nodes of NAND gates (30-37), sub shift registers (40-41) controlled by the output signal of the NAND gates are connected sequentially for synchronous signals to be shifted for output from the shift register

Machine guard system

Abstract: PURPOSE:To considerably improve the reliability of time data added to sensor operation information by calibrating the time of a clock device provided in a first device based on time information from a time information supply device provided in a second device at each time of communication to the second device. CONSTITUTION:Terminal equipments T1 to Tn and a monitor center 4 are connected by lines, and times of clock devices of terminal equipments are calibrated based on time information from a master clock device 18. That is, the time of each of terminal equipments T1 to Tn is equalized to the time of the master clock device 18 each time when the terminal equipment is connected to the monitor center 4 by the communication line by some cause. Therefore, data related to operation conditions of sensors stored in RAMs of terminal equipments are easily compared, and settlement of trespass process of a intruder, discrimination of operation defects and faults of sensors, etc., are easily performed. Consequently, the movement condition of the intruder is easily and accurately recognized.

Serial/parallel conversion circuit

Abstract: PURPOSE:To decrease the number of circuit element and to reduce the circuit scale of a serial/parallel conversion circuit. CONSTITUTION:The n-stage shift registers 23 and 24 successively shift the input signals by a master clock. The selectors 21 and 22 select the input signal in place of the n-i stage outputs of the registers 23 and 23 in a (i0

Clock regenerating circuit

Abstract: PURPOSE:To provide the clock regenerating circuit with short synchronization pull-in time and insusceptible to effect of jitter with respect to the clock recovery circuit recovering a clock signal subjected to phase synchronization with an input signal. CONSTITUTION:The circuit is provided with a 1/N frequency division counter means 14 frequency-dividing a master clock to generate, a phase adjustment means 4 discriminating a lead/lag of a phase of the recovered clock with respect to the input signal an generating the master clock whose number of pulses is controlled so that the recovered clock approaches a phase of the input signal by a 1/N clock period per one recovered clock period based on the result of discrimination, and a reset means 5 detecting a phase difference between the input signal and the regenerated clock and resetting forcibly the 1/N frequency division counter 14 so that the phase of the recovered clock is synchronously with the phase of the input signal at a succeeding recovery clock period when the phase difference exceeds a prescribed inspection range.

Phase correction value storage type clock reproducing circuit

Abstract: PURPOSE:To provide a phase correction value storage type clock reproducing circuit which can generate the reproduction clocks corresponding to each station with a single clock reproducing circuit despite a large number of stations that receive the burst data. CONSTITUTION:A phase comparator 2 compares the phase of the burst reception data received from each station in time division with the phase of the clock obtained by dividing a master clock by a variable divider 1. Based on this comparison result, a clock inserting/deleting part 3 inserts or deletes the clock to correct the phase and generates a reproduction clock synchronous with the burst reception data from the output of the divider 1. The phase correction value set by the clock inserting/deleting frequency is stored in a memory corresponding to each station of a phase correction value memory part 30 when the reproduction clocks of plural stations are generated by a clock reproducing circuit 20. Then the phase correction value stored in the memory is loaded into the divider 1 of the circuit 20 when the burst signal is received from each station. Then the phase of the clock to be inputted to the divider 1 is varied by an extent equal, to the phase correction value, and the reproduction clocks are generated by the circuit 20.

Equipment and method for starting of multiprocessor system

Abstract: PURPOSE: To provide an architecture and method for starting a multiprocessor system equipped with a processor local memory and a shared global memory. CONSTITUTION: Access to a shared global memory is managed by an atomic memory access controller, and the coherence of a cache memory is managed by software. A common start signal and the individual restart procedure of a processor are synchronized with a master clock by using a reset circuit. Also, a reset circuit signal is distributed for resetting both local and global memories. The test of the global memory is assigned to one certain processor according to the situation of progress at the implementation of an inside test procedure, and executed. This system and method is suitable to the start of a multiprocessor system constituted of a plurality of processors which can be individually and independently operated.