Showing papers on "Master clock published in 2005"

Clock distribution network using feedback for skew compensation and jitter filtering

Abstract: A clock distribution network for clock distribution in an integrated circuit (IC) using digital feedback for skew compensation and jitter filtering. In an embodiment, a number of clock processor nodes are distributed throughout the clock distribution network on the IC at respective local clock regions. A master clock generator generates a master clock for distribution to the clock processor nodes, via the clock distribution network, to compensate clock skew and filter clock jitter locally at the respective local clock regions.

Method and apparatus for aligning time references when separated by an unreliable data packet network

Abstract: A time control mechanism accepts samples of time (true or otherwise) (101) over a network, and enables dynamic compensation for random delays of the network (105 and 106) in order to maintain the output of a slave clock (1029 that the time control mechanism controls within required bounds relative to the time of a master clock, even when the samples are randomly delayed. In one embodiment, a hardware timestamping method and apparatus is provided. The hardware timestamping method and apparatus is used to achieve the fine resolution required for timestamping both received samples and transmitted requests. In another embodiment, a delay-variation-smoothing method and apparatus is provided. The delay-variation-smoothing method and apparatus allows the time control mechanism to calculate the network delay in order to maintain the slave clock within the required time bounds. Moreover, a method and apparatus is provided that not only compensates for the random delays in the samples but also dynamically adjusts its operations to suit the changing characteristics of the delay path (typically a network).

Method and apparatus for generating a sequence of clock signals

Abstract: A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input by a plurality of respective delays. Two of the clock signals in the sequence are applied to a phase detector so that the signals at the outputs of the delay line have predetermined phases relative to each other. The outer delay-locked loop is formed by a voltage controlled delay circuit that delays the command clock by a voltage controlled delay to provide the reference clock to the delay line of the inner delay-locked loop. The outer delay-locked loop also includes a phase detector that compares the command clock to one of the clock signals in the sequence generated by the delay line. The outer delay-locked loop thus locks one of the clock signals in the sequence to the command clock. As a result, all of the clock signals in the sequence generated by the delay line have respective predetermined phases relative to the phase of the command clock. One of the clock signals in the sequence is selected by a multiplexer to clock a command data latch at a time corresponding to the delay in coupling a command data bit to the latch.

AD conversion method, AD converter, semiconductor device for detecting distribution of physical quantities, and electronic apparatus

Abstract: In a solid-state imaging device including an analog-to-digital converter, a clock converter that generates a high-speed clock that is faster than a master clock is provided. A voltage comparator compares a pixel signal input from a vertical signal line for each row control line with a reference voltage, generating pulses having magnitudes corresponding to a reset component or a signal component in a temporal direction. A counter counts the width of pulse signals until completion of the comparison in the voltage comparator based on a clock that is generated based on the high-speed clock, holding a count value at a time of completion of the comparison. A communication and timing controller exercises control so that the voltage comparator performs comparison for the reset component and the counter performs down-counting in a first processing iteration and so that the voltage comparator performs comparison for the signal component and the counter performs up-counting in a second processing iteration.

Method and apparatus for synchronizing clock timing between network elements

Abstract: Network elements may be synchronized over an asynchronous network by implementing a master clock as an all digital PLL that includes a Digitally Controlled Frequency Selector (DCFS), the output frequency of which may be directly controlled through the input of a control word. The PLL causes the control word input to the master DCFS to be adjusted to cause the output of the master DCFS to lock onto a reference frequency. Information associated with the control word is transmitted from the master clock to the slave clocks which are also implemented as DCFSs. By using the transmitted information to recreate the master control word, the slaves may be made to assume the same state as the master DCFS without requiring the slaves to be implemented as PLLs. The DCFS may be formed as a digitally controlled oscillator (DCO) or as a Direct Digital Synthesizer (DDS).

Organization of endogenous clocks in insects.

Abstract: Insect and mammalian circadian clocks show striking similarities. They utilize homologous clock genes, generating self-sustained circadian oscillations in distinct master clocks of the brain, which then control rhythmic behaviour. The molecular mechanisms of rhythm generation were first uncovered in the fruit fly Drosophila melanogaster, whereas cockroaches were among the first animals where the brain master clock was localized. Despite many similarities, there exist obvious differences in the organization and functioning of insect master clocks. These similarities and differences are reviewed on a molecular and anatomical level.

Method and apparatus for synchronizing internal state of frequency generators on a communications network

Abstract: A first level of control over operation of slave Digitally Controlled Frequency Selectors (DCFSs), such as DCOs or DDSs, may occur by periodic transmission of control words from the master clock to the slave clocks. To allow enhanced control over the output of the slave clocks, the frequency of the local oscillator used to generate the synthesized output of the master clock may also be conveyed to the slave clocks to allow a second level of control to take place. The second level of control allows the local oscillators at the slave clocks to lock onto the frequency of the master local oscillator to thereby allow the slave local oscillators to operate the slave DCFSs using the same local oscillator frequency. The first level of control synchronizes operation of the DCFSs while the second level control prevents instabilities in the local oscillators from causing long term drift between the slave and master clock outputs. Timestamps may be used to synchronize the master and slave local oscillators.

Clock distribution network supporting low-power mode

Abstract: A clock distribution network locks a local clock signal to a reference clock signal using a first feedback loop associated with a synchronization circuit (e.g., a PLL or a DLL). The local clock signal can then be selectively distributed to a plurality of clock destination nodes via a clock network. Clock distribution may be disabled as needed to save power. The first feedback loop is active irrespective of whether clock distribution is enabled. The delay through the clock network may drift due to temperature and supply-voltage fluctuations, which introduces phase errors in the distributed clock signals. A second feedback loop is activated when clock distribution is enabled to compensate for this drift.

Communication system and synchronization method thereof

Abstract: A clock signal of a master clock of a sender is transmitted to a receiver through a classical channel and is returned from the receiver. The clock signal is transmitted with strong light from a sender-side quantum unit to a receiver-side quantum unit through a quantum channel. A sender-side synchronization section establishes phase synchronization between the clock signal returned from the receiver and the clock signal detected by the sender-side quantum unit, and generates a calibration clock signal. At the receiver as well, a receiver-side synchronization section establishes phase synchronization between the clock signal detected from the classical channel and the clock signal detected by the receiver-side quantum unit, and generates a calibration clock signal.

System and method for synchronizing audio-visual devices on a power line communications (PLC) network

Abstract: A method and apparatus for synchronizing streaming media devices within a PLC network. Output synchronization errors exceeding ˜30 ms become noticeable when multiple streaming media devices are outputting an audio stream. The present invention provides a system and method for isochronously sending periodic reference clocks from a master device to client devices coupled to the PLC network. The client devices set their clocks based on the reference clock. In addition the clients adjust their system clock time base in response to the average divergence of the system clock with the reference clock, or a count of the number of clocks between beacon frames. In this way the client clock is adjusted to closely track the server clock so that synchronization is maintained between each of the devices. Streaming audio shared between servers and client devices is thus output across the network with high fidelity due to the accurate synchronization.

Low-energy sensor network time synchronization as an emergent property

Abstract: The primary contribution of this work is to examine the energy efficiency of pulse coupled oscillation for time synchronization in a realistic wireless network environment and to explore the impact of mobility on convergence rate. Energy coupled oscillation is susceptible to interference; this approach uses reception and decoding of short packet bursts to eliminate this problem. The energy efficiency of a commonly used timestamp broadcast algorithm is compared and contrasted with pulse-coupled oscillation. The emergent pulse coupled oscillation technique shows greater energy efficiency as well as robustness with mobility. The algorithm specifically includes the likelihood that some proportion of the sensors may include GPS receivers in order to obtain and propagate a master clock time.

Method and system for synchronizing separated edge qam devices located remotely from a cmts

Abstract: The clocks of one or more edgeQAM (58A) devices are synchronized with a master clock (12) at the remotely located CMTS (8). A master clock signal may be transmitted via a dedicated gigabit Ether link (6). Alternatively, master clock information contained in a time synchronization message may be transmitted for use in adjusting local oscillators (68A) that drive local clocks (14) at respective edgeQAM devices (58 a...n).

Phase alignment method for master and stand-by clocks

Abstract: A phase alignment method for master and standby clocks is that a standby clock locks the master clock or a same reference source with the master clock by a phase detector, a signal processor and a direct frequency synthesizer(DDS) to let the master and standby output the same frequencies. The phase difference judgment is carried out to master and standby clocks to regulate the standby output phase to align their phases, the phase detection value output by the phase detector is compensated based on the phase difference so that the standby output phase regulation does not influence its lock to the reference source.

Redundant synchronous clock distribution system

Abstract: A redundant synchronous clock distribution system is provided comprising at least a first and a second clock module and first and second clock distribution branches adapted for synchronizing at least one clock slave module connected downstream to the redundant synchronous clock distribution system. Each of the first and second clock modules are adapted to act as a master clock module or a slave clock module. A clock switchover module is adapted to switch each of the first and second clock modules to change between the master mode and the slave mode. The clock switchover module comprises a flip-flop-circuit having a first circuit part and a second circuit part, wherein the first circuit part is located on the first clock module and the second circuit part is located on the second clock module.

Data transfer memory

Abstract: A data transfer memory for reducing the number of components in an electronic module. A master controller circuit provides a transfer start command to a master clock signal generator circuit when receiving an activation detection signal from a power activation detection circuit. As a result, the master clock signal generator circuit generates a basic clock signal, outputs the basic clock signal to an SCL line, and has a master transfer sequencer circuit execute a transfer sequence. The master transfer sequencer circuit transmits a start condition, data stored in the nonvolatile memory via a serial control circuit, and a stop condition to an SDA line synchronously with the basic clock signal.

Wireless clock system and method

Abstract: A wireless clock system includes a master clock or other master time source, and a plurality of slave clocks or repeater devices. Each slave clock can both wirelessly receive and wirelessly transmit time signals including current time data. To avoid conflicts among the slave clocks, each slave clock transmits time signals in a frequency-hopping manner over pseudo-randomized frequencies and at pseudo-randomized transmission start times. In another embodiment, power consumption at the slave clocks is minimized by activating and deactivating receivers within the slave clocks at predetermined times and at predetermined intervals, each interval being longer than the previous interval, until valid time signals are received from either the master clock or another slave clock. Calibration of the slave clock's time base is also performed.

Phase Noise Characteristics of Fiber Lasers as Potential Ultra-Stable Master Oscillators

Abstract: Fourth-generation light sources, such as the European X-Ray Free Electron Laser facility (XFEL), require timing signals distributed over distances of several kilometers with a timing jitter in the order of femtoseconds. The master clock for the proposed optical distribution system must operate with exceptionally low timing jitter. A promising approach is the use of a mode-locked laser that generates ultrastable pulses which are distributed via timing stabilized fiber links. Mode-locked Erbium-doped fiber lasers are attractive candidates, featuring very low noise at high frequencies. In this paper, we present a study of the phase noise of various mode-locked fiber lasers in view of their applicability as laser-based master oscillators for femtosecond-level timing distribution.

Analysis of a discrete network synchronization algorithm

Abstract: Mobile communication systems benefit from synchronous networks. This is especially important if the system also offers positioning services that are often asked nowadays. In this work we analyze a discrete terrestrial network synchronization algorithm. It is analytically shown that the algorithm provides synchronism in its different modes. In the mutual synchronization mode the time varies around the theoretical mean value with an increasing variance, i.e., the system's time intervals vary with time. In the master based mode variations are limited if the master clock has a high quality. However, if the times are compared to a time of a selected reference node, the covariance remains limited which affirms usability of the algorithm. In the simulations the convergence speed of the algorithm is studied for various system parameter values. In addition, also the effects of non-idealities are studied showing, e.g., that the algorithm tends to limit the effects of clock frequency error and drift

Apparatus and method for transmitting data by radio

Abstract: An apparatus for transmitting data by radio to a receiver is described. The apparatus comprises a controller having an input for receiving data; a local clock forming part of a phase locked loop adapted to be synchronised at predetermined intervals to a master clock signal; and a time stamp circuit adapted to add time stamp data from the local clock to the data to form time stamped data. The apparatus also comprises a transmitter circuit adapted to receive the time stamped data and to transmit the time stamped data by radio to the receiver. The phase locked loop allows the local clock to remain in synchronism with the master clock without requiring the master clock to be read for each item of data transmitted. This enables a more efficient use of hardware resources. A wireless sensor, wireless telemetry system and method of transmitting data is also disclosed.

Optimal clock synchronization under energy constraints in wireless ad-hoc networks

Abstract: Clock synchronization is a crucial service in many distributed systems, including wireless ad-hoc networks This paper studies external clock synchronization, in which nodes should bring their clocks close to the value of some external reference time, which is provided in the system by one or more source clocks Reference broadcast synchronization (RBS) is a known approach that exploits the broadcast nature of wireless networks for a single hop However, when networks are large in physical extent, additional mechanisms must be employed Using multi-hop algorithms that re-broadcast time information to short distances reduces the energy consumed for clock synchronization The reason is that energy costs grow more than linearly with the broadcast distance On the other hand, the quality of the clock synchronization, as measured in the closeness of the clocks, deteriorates as the number of hops increases This paper shows how to balance these two contradictory goals, achieving optimal clock synchronization while adhering to an energy budget at each node In particular, a distributed algorithm is presented that uses multi-hop broadcasting over a shallow infrastructure to synchronize the clocks The closeness of clock synchronization achieved by the algorithm is proved to be optimal for the given energy constraints

Method and apparatus for assigning addresses to users of a bus system

Abstract: Method for addressing slave members of a master-slave bus system in which a slave (14-1, 14-n) that has a bus clock signal applied to its clock input (26) is addressed by the master, after addressing the slave microprocessor (22) generates a confirmation signal that is logically linked with the clock signal and causes a switching of the clock signal to the clock output (28). The preceding steps are applied until all slaves have been addressed. An independent claim is made for a master-slave bus system.

Systems and methods for clock mode determination utilizing divide ratio testing

Abstract: A system for determining a data converter operating mode includes measurement circuitry for measuring master clock frequency of a master clock signal and a frequency ratio between a frequency of a data clock signal and the master clock frequency and a mapping system for mapping the measurement of the frequency ratio to an operating mode of the data converter. The mapping system generates a set of candidate divide ratios for dividing the master clock frequency to generate corresponding internal master clock frequencies of an internal clock signal and determines the lowest divide ratio which generates a supported internal master clock frequency. In an alternate embodiment, the mapping system determines the divide ratio required by a filter of the data converter by dividing the data clock to master clock frequency ratio by a data clock to internal clock frequency ratio between the data clock frequency and the frequency of an internal clock signal. In additional embodiments, the mapping system gives preference to natural number divide ratios during mode mapping.

Multi mode clock generator

Abstract: In some embodiments, a clock generator is provided that provides a generator clock. The clock generator comprises a first clock source to provide a first clock and a second clock source to provide a second clock whose frequency at least indirectly tracks a supply to a clock distribution network. The clock generator selectably provides as the generator clock the first clock when the second clock leads the first clock and the second clock when it lags behind the first clock. Other embodiments are claimed and disclosed herein.

Clock distribution for interconnect structures

Abstract: Some embodiments of the invention include an interconnect structure having a plurality of connector circuits to transfer messages among a number of devices. Each of the connector circuits includes a data transfer unit to transfer messages and a clock unit to provide timing to transfer the messages. The interconnect structure propagates a master clock signal serially through the clock units of the connector circuits to generate a number of different input clock signals. The timing provided by each of the clock units is based on the timing of one of the input clock signals. Other embodiments are described and claimed.

Systems and methods for clock mode determination utilizing a fixed-frequency reference signal

Abstract: A system for determining a data converter operating mode including measurement circuitry operable to measure a master clock frequency by comparing a frequency of a master clock signal and a frequency of a fixed frequency clock signal and operable to measure a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In one particular embodiment, the fixed frequency clock signal is provided by an oscillator. In a further embodiment, the master clock signal is generated by multiplying the frequency of another clock signal.

Clock distributor for use in semiconductor logics for generating clock signals when enabled and a method therefor

Abstract: A clock distributor circuit is provided which works with power consumption reduced in semiconductor logic circuitry including clock synchronous circuits. The clock distributor circuit includes clock generation circuits generating gated clock signals in response to a clock enable signal to supply clock synchronous circuits with the generated clock signals. It is thus possible to reduce the power that would otherwise consumed by the toggling of the clock signal. A clock distribution method therefore is also provided.

Clock generation device and clock generation method

Abstract: Upon reception of digital broadcast, system clocks which follow PCR data of an MPEG2-TS are provided. Upon disc playback, system clocks as fixed clocks are provided. To this end, upon processing the MPEG2-TS, first clocks CK 1 synchronized with the PCR data are generated. If the user designates playback using high-precision clocks, third clocks CK 3 as fixed clocks are generated. If the user does not designate any high-precision clock playback, clocks CK 1 are generated. When use of clocks CK 1 is stopped, clocks CK 3 are generated after second clocks CK 2 synchronized with clocks CK 3 are mediated.

Timing System for J-PARC

Abstract: J-PARC has three accelerators running at the different repetition rates; a 400-MeV linac (50Hz), a 3-GeV rapid cycling synchrotron (RCS, 25Hz), and a 50-GeV synchrotron (MR). The linac and the RCS deliver the beam pluses to the different destinations in each cycle. The destinations are scheduled according to the machine operations. We define two kinds of timing, "scheduled timing" and "synchronization timing" so that the accelerators are operated with proper timing and the beam pulses are transported to the experimental facilities or the next accelerators. The J-PARC complex requires a stable and precise timing system. The system is based on a master clock generated by a synthesizer and the triggers are operated independently of the AC-line frequency. We describe the design of the J-PARC timing system and their configuration, and also present the hardware details.

Support for x-ray equipment

Abstract: Network elements may be synchronized over an asynchronous network by implementing a master clock as an all digital PLL that includes a Digitally Controlled Frequency Selector (DCFS), the output frequency of which may be directly controlled through the input of a control word. The PLL causes the control word input to the master DCFS to be adjusted to cause the output of the master DCFS to lock onto a reference frequency. Information associated with the control word is transmitted from the master clock to the slave clocks which are also implemented as DCFSs. By using the transmitted information to recreate the master control word, the slaves may be made to assume the same state as the master DCFS without requiring the slaves to be implemented as PLLs. The DCFS may be formed as a digitally controlled oscillator (DCO) or as a Direct Digital Synthesizer (DDS).

Systems and methods for clock mode determination utilizing operating conditions measurement

Abstract: A system for determining a data converter operating mode includes measurement circuitry which measures a master clock frequency, measures a frequency ratio between a frequency of a data clock signal and the master clock frequency, and measures a selected operating condition of the data converter. A mapping system maps the measurements of the master clock frequency, the frequency ratio, and the selected operating condition, to an operating mode of the data converter. In another embodiment, the measurement circuitry adjusts the measurement of the master clock frequency in response to a measurement of the operating conditions of the data converter. In a further embodiment, user input information varies the measurement of the master clock frequency.