Showing papers on "Memory controller published in 1984"

Solid state memory for aircraft flight data recorder systems

Abstract: A memory unit for a aircraft flight data recorder system uses an electronically erasable solid state memory for storing the flight data and a memory controller circuit are housed in a penetration resistant, thermally insulated enclosure. Power dissipation within the insulated enclosure is minimized by an external switching circuit that applies operating potential to the solid state memory only when data are being transferred to and from the memory circuit. A data protection circuit, located within the insulated enclosure inhibits memory write and erase operations whenever the system operating potential falls below a predetermined level. In continuously storing flight data, the oldest stored data is overwritten with newly arriving flight data and the memory controller maintains an erased boundary that defines the beginning and end of the recorded data. A power monitor circuit, located outside the insulated enclosure, resets the memory controller to the erased boundary following a power interruption. A dedicated portion of the memory space is utilized to store the address of faulty memory locations (detected during the data storage sequence) and stores the beginning and ending memory address of selected portions of the data record. The memory controller is sequenced to skip both the faulty memory locations and memory storage locations associated with the selected portions of the data record when new flight data is being stored.

Pipelined single chip microprocessor having on-chip cache and on-chip memory management unit

Abstract: A 32-bit central processing unit having a six-stage pipeline architecture with a cache memory and memory management unit all provided on a single integrated circuit (I.C.) chip but without any peripheral interface input/output circuits, clock or similar circuits on the chip in order to utilize the limited I.C. area for implementing the processor functions that most directly affect speed of operation and other performance factors.

Direct memory access controller supporting multiple input/output controllers and memory units

Abstract: A direct memory access controller (8, FIG. 1) is provided which can service a number of input/output controllers (24, 26) concurrently on a time-division multiplexed basis. The direct memory access controller 8 (DMAC) is capable of interconnecting more than one input/output device (64, 66, 69, 74, 76) with more than one system memory (2, 20). The DMAC 8 can also transfer data from one system memory (2) to a second system memory (20), or within one system memory.

Apparatus for controlling access to a memory

Abstract: A computer system having a central processing unit, a dynamic memory controller, an error detection and correction network and a dynamic memory for storing data that are subject to being refreshed and to data bit errors. The dynamic memory controller has a refresh mode for controlling access to the memory only to refresh the data, a refresh with error detection and correction mode, for controlling access to the memory to merge or simultaneous refresh a row of data while detecting and correcting data bit errors, and a read/write mode for controlling access to the memory in response to CPU requests for a read/write memory operation.

Single chip dram controller and CRT controller

Abstract: A video memory and display (CRT) controller circuit on a single semiconductor substrate controls a DRAM (dynamic random access memory) used as a video memory and a CRT display. The video memory and display controller is normally a part of a video system which includes a data processor, video memory and a CRT display. The video memory and display controller includes a row address latch for storing a row address, a column address latch for storing a column address, display address logic which generates row and column addresses for display update ad refresh logic which generates row addresses for the required periodic DRAM refresh. A multiplexer provides the application of the proper address to the address bus of the DRAM. The display controller circuit is responsive to the data processor data bus for generating display control signals for control of the CRT display.

Data processor system having improved data throughput in a multiprocessor system

Abstract: A data processor system includes a plurality of multiprocessor systems, and each multiprocessor system is connected through each memory control unit of each multiprocessor system. Each multiprocessor system comprises a memory control unit, at least one central processing unit, at least one channel control unit, and at least one main memory unit. The central processing unit, channel control unit, and main memory unit are connected to the memory control unit via interface lines. The memory control unit comprises at least two pipelines and at least two access requests to the main memory unit belonging to the pipe-line, and the other pipe-line is used for access requests to another main memory unit belonging to another memory control unit.

Memory-programmable controller

Abstract: A memory-programmable multiprocessor controller having a word processor and a bit processor is disclosed. The word processor is coupled to a separate peripheral bus for providing communication with a peripheral module coupled to the process being controlled. An internal system bus separated from the peripheral bus provides communication between the bit processor, user program memory and data memory. The bit processor accesses the user program memory and the data memory via separate dedicated buses. Rapid command execution can thereby be achieved.

Method of internal self-test of microprocessor using microcode

Abstract: A microprocessor device is used in an adapter for a communications loop of the closed ring, one-way, token-passing local area network type. Each station has a host processor with a host CPU, a main memory, and a system bus, and has an adapter including the microprocessor tested according to the invention. The adapter coupled to the main memory by the system bus and includes a local CPU (the microprocessor), a local read/write memory, and a local bus. A transmit-and-receive controller is coupled to the local bus to directly access the local read/write memory; when this station receives a free token, the transmit-and-receive controller copies the message frame to be transmitted from the local read/write memory to the outgoing signal path, converting from parallel to serial. When a message addressed to this station is received, the controller converts it from serial to parallel, and copies the message frame into the local read/write memory via the local bus. Testing of the microprocessor is accomplished by internal self-test of the registers of the device, using the microcode of the control ROM initiated by a test control input.

Video memory controller

Abstract: A video memory controller controls a DRAM (dynamic random access memory) used as a video memory and as a system memory. The video memory and the video memory controller are normally a part of a video system which includes a data processor, the video memory, the video memory controller, a CRT controller and a CRT display device. The video memory controller includes a row address latch for storing a row address from the data processor, a column address latch for storing a column address from the data processor, a refresh address register for storing a memory refresh address and a display update generator for sequentially generating the addresses necessary for update of the CRT display. A multiplexer couples the proper address to the video memory under control of a memory cycle generator which generates the timing of the memory refresh and display update. An arbiter device enables only one of the possible memory cycles at a time. The data processor has higher priority over memory refresh during an initial period of each horizontal line of the display, while the memory refresh has higher priority over the data processor during the final period of each horizontal line.

Single chip video system with separate clocks for memory controller, CRT controller

Abstract: A video system has a controller for controlling the transfer of data from a processor to a CRT monitor. The controller has two clocks and a CRT interface for synchronously interfacing the controller to the CRT monitor, a second interface for synchronously interfacing the controller to the processor. A first clock source provides timing for the CRT interface and is in synch with the timing of the CRT monitor. A second clock source provides timing for the processor interphase which is in synch with the timing of the processor.

Microprocessor device with integrated auto-loaded timer

Abstract: A microprocessor device with an on-chip integrated auto-loaded timer is used in an adapter for a communications loop of the token-passing local area network type. The network has a number of stations coupled to a closed one-way signal path, and each station has a host processor with a host CPU and memory. The microprocessor device with integrated auto-loaded timer is part of an adapter coupled to the host processor. A message frame to be transmitted is copied into a local read/write memory in the adapter by way of the host system bus and a local bus, under initiation by the host CPU. A transmit-and-receive controller is coupled to the local bus to directly access the local read/write memory; when this station has access to the loop (i.e., receives a free token) the transmit-and-receive controller copies the message frame from the local read/write memory to the outgoing signal path, converting from parallel to serial. When the transmit-and-receive controller receives a message addressed to this station, it converts it from serial to parallel, and copies the message frame into the local read/write memory via the local bus, interrupting the local CPU. The message frame is then copied from the local read/write memory to the main memory.

A 32b microprocessor with on chip virtual memory management

Abstract: The development of a 140,000 transistor 32b single chip microprocessor, implementing a superminicomputer's 304 instructions will be described. The chip is 8.5 × 8.0mm and dissipates 3W.

Information processing system

Abstract: PURPOSE:To relieve the load of the hardware by providing a memory access interface between memory controllers so as to decrease the number of memory access interfaces in the entire system in a system of multiprocessor constitution CONSTITUTION:The memory access interface (MAIF) 300 is provided newly between the memory controllers 110 and 210 When an operation controller 150 requires the memory access to a data corresponding to a main storage device 200, the access request is attained to the memory controller 110 to which the MAIF is connected When the conroller 110 detects that this access request is the access to the data corresponding to the main storage device 200, the memory access request to the controller 210 is performed via the MAIF 300 The controller 210 accesses a cache memory 215 or the main storage device 200 the same as a conventional controller In case of the data read, the read data is transmitted to the operation controller 150 requesting the memory access via the controller 110 and the MAIF 300

Still picture signal reproducing device

Abstract: PURPOSE:To simplify the constitution of a reproducing device for a disk, etc, and to increase storage capacity by making the rotation of the disk constant, storing one-screen data in a memory temporarily, and reproducing a still picture by a suitable clock CONSTITUTION:This reproducing device consists of a driving means 2 which rotates the optical disk 1, etc, at a constant rotating speed, a pickup 4 which reads a signal out of the disk 1, etc, the memory 11 wherein the output of the pickup 4 is stored temporarily, a demodulating means 17 which demodulates and outputs the output of the memoryf 11 to an output device, a timing signal detecting circuit 6 which detects the timing signal in the output of the pickup 4, a memory controller 9 which stores one-screen data on a still picture signal in the memory in responding to the output of the circuit 6 and then outputs it to the timing means 17 at timing matching with the output device, etc Consequently, the constitution is simplified, high-speed access is realized, and the recording capacity is increased

A memory circuit having a memory reset and recovery controller

Abstract: A memory circuit for storing data words including a core memory (16) having a matrix (M) of rows (R) and columns (C) of core cells (CC) which store bits of the data words, a row address decoder circuit (22) for driving the rows, and a control signal generator (46), operative over one reset period and one recovery period, for controlling the columns and the row address decoder circuit to simultaneously charge the contents of the entire core memory to one data state.

Memory fault correcting system

Abstract: PURPOSE:To prevent the data processing ability from being deteriorated by changing over a mode into a memory alternate mode as a fixed fault when a data corrected by an error detection and correcting means is taken as the error again and executing the processing correcting an error bit and copying it to an alternate memory at the interval of data processing. CONSTITUTION:The error detecting signal Sa of an error correcting code forming and check circuit 9 is fed to a memory controller 13 and an error detecting signal Sb is fed to a processor CP. The operation of the processor CP is executed not by the program of a main memory 3 but by a microprogram of the processor CP when the signal Sb is received. If an fixed fault occurs in the sub- blocks 3-1-1--39 of the main memory 3, the alternate memory 4 corresponding to the block takes over the block. Then, the location of a fixed fault bit is stored in a storage register group 5 corresponding to the blocks 3-1-3-4. When the block including the fixed fault is the 3-2-l, the information to be given to the block 3-2-l is copied to the alternate memory 4-2 as to all addresses of the block 3-2. In order to prevent the intermission of data processing during the memory alternate operation, the memory alternate operation is executed one by one word at the refresh of memory.

Buffer memory control system

Abstract: PURPOSE:To reduce the transmission of invalidity requests of cache by deciding with the reference processing whether the contents of a region corresponding to the cache of a central processor of another information processing system is invalidated or not and then delivering an invalidity request when necessary CONSTITUTION:The data of an intermediate buffer memory of another information processing system is supplied from a terminal A; the data of a central processor is supplied from a terminal J; and the data of a main storage device is supplied from a terminal R These data are stored in a register 16 and then an intermediate buffer storage data part 17 The addresses indicated by the intermediate buffer memory controller and the central processor are supplied to a register 11 from terminals B and D respectively Then the signal showing whether the requests, ie, the fetch, store and invalidity requests of the intermediate buffer memory controller of another system are hit or not is supplied to a control circuit 15 from a terminal C While the same requests of own system are delivered to the intermediate buffer memory controller from a terminal L

Diagnosis system of ecc circuit

Abstract: PURPOSE:To diagnose an error detection and correction circuit at memory accesing of 1/m-word and to improve the resolution of error, by providing a check bit in the memory data unit of 1/n-word CONSTITUTION:A memory array 21 stores the high-order 1/2-word among memory data when n=2, and a memory array 22 stores similarly the low-order 1/2- word The check bit C is added to the memory data of each 1/2-word Error detection and correction ECC circuits 31, 32 perform error detection based on the inputted 1/2-word and the check bit C for attaining error correction In case of the readout of 1/m-word, the desired bit is inputted to both the ECC circuits 31, 32 with the control of a memory controller 30 A comparison circuit COMP33 compares signals outputted from the ECC circuits 31, 32 and detects coincidence/ dissidence

Accumulating and reproducing device of facsimile

Abstract: PURPOSE:To prevent the reduction of transmission speed of a facsimile by storing picture information with a large amount of data in a volatile memory and also storing only control data with a small amount of data in a non-volatile memory. CONSTITUTION:A picture signal is applied to a code compressing part 5 through switches 3, 4 to be controlled by a system controller 2, the encoded output is modulated by an MODEM 7 and the modulated signal is sent from an automatic dialing device 8 to a transmission line. The signal from the transmission line is demodulated by the MODEM 7, the demodulated signal is converted into a picture signal by the compressing part 5 and the converted signal is applied to a printer 11 through switches 9, 10. A facsimile accumulating/reproducing device B is connected to a facsimile body part A and a memory controller 13 in the device B is controlled by an operating part 12 connected to a controller 2. The controller 13 stores the picture information with a large amount of data in a volatile main memory 17 and the control data with a small amount of data in a control data memory 14, so that the data are accumulated and reproduced without reducing transmission speed.

Communication system between computer systems

Abstract: PURPOSE:To attain the communication between computer systems by providing a communication means to perform the communication between service processors each other to the service processor which executes the operation and maintenance/diagnosis for each partition of a computer system containing plural partitions. CONSTITUTION:A means performing the communication between serice processors is provided to service processors 1 and 1' which execute the operation and maintenance/diagnosis for each partitions 6 and 7. For instance, if a fault arises at one of a memory controller 2, a memory 3, a central processing unit 4 and a channel controller 5 of the partition 6, the function of the partition 6 is discontinued and switched to the partition 7. However the processor 1 of the partition 6 is operative and therefore can transfer various types of information so far stored to the processor 1' of the partition 7.

Memory controller having data rotation unit

Abstract: A memory unit for connection in a data processing system in which the central processor unit may transfer data to or retrieve data from portions of two storage locations in one transfer. The memory unit has a data rotating and storage network that rotates the data and stores it as necessary for its transfer to or from the addressed storage locations.

Buffer memory controller

Abstract: PURPOSE:To avoid deteriorating the performance of a buffer memory although some of the blooks of the buffer memory has a fault by making the information corresponding to the disable block correspond to another available block when a part of blocks in a buffer memory is disable state. CONSTITUTION:When an access is given to the data in a column 2 of a large- capacity memory 20, an address converting part 60 has no conversion of column address since both rows 1 and 2 are not disable state for the block in the column 2. Thus block (c) and (d) of the column 2 of address arrays 11 and 12 are read out as they are and compared with a comparison address A through comparators 31 and 32. When the coincidence is obtained the contents of with the block (c) or (d), the data sent from a data array 81 or 82 of the row number at the coincident side is selected. If no coincidence is obtained with the contents of both blocks (c) and (d), a desired block is loaded to either one of blocks in the column 2 of the buffer memory from the memory 20.

A 5V-only single chip microcomputer with nonvolatile SRAM

Abstract: An 8b single chip microprocessor with a memory containing 32Kb of ROM, 512b of RAM and 512b of nonvolatile SRAM, implemented in 4μm double poly floating gate technology, will be described.

Input and output processing system by memory access instruction

Abstract: PURPOSE:To perform the input/output processing with a memory access instruction, by using with high efficiency an address conversion table which is indispensable to an information processor which performs a memory access after converting a logic address into a physical address CONSTITUTION:When the page shown by a page number PN on a logic address is defined on a main memory, an illegal bit Ir is set at logic ''0'' In the case of Ir=''0'', a memory controller performs a memory access by means of a memory read/write signal R/W and a generated physical address When the page shown by the number PN is not defined on the main memory, the bit Ir is set at logic ''1'' Then the memory controller performs no memory access in the case of Ir= ''1'' In other words, the corresponding memory access instruction is used as an input/output instruction by making use of a fact that the memory controller has no memory access operation even with a memory access instruction

Parity checking system of memory

Abstract: PURPOSE:To prevent the misdetection of parity errors due to noises, etc. by holding the state of a memory controller when a parity error is detected and then retrying the parity check. CONSTITUTION:A memory controller 2 detects the information on generation of a parity error which is sent from a parity checking circuit 4 and then sets a flip-flop 5 for parity check without delivering an ACK signal to a CPU to hold the state of that time point. Then the controller 2 reads the same data out of a memory 1 and then performs the parity check again through the circuit 4. If no parity error is detected, the controller 2 resets the flip-flop 5 to release the holding of retry states of hitherto parity checks. Then the controller 2 delivers the ACK signal to the CPU and at the same time transfers the holding data to a latch 3. As a result, the parity error that is previously detected is regarded as misdetection due to noises, etc. and this misdetection is recovered.

Outputting method to external device

Abstract: PURPOSE:To shorten the occupation time of an external device and to improve an output processing speed by storing data to be outputted in a buffer memory temporarily, and outputting the contents of the buffer memory when next data is not generated within a specific time under timer control. CONSTITUTION:When data from an input device 1 is inputted, a memory controller 2 stores the data in the buffer memory 3 and starts a timer circuit 4. Then, the circuit 4 is reset every time data is inputted and when there is no input within the specific time, an output control circuit 5 is started. Consequently, the circuit 5 outputs the stored data to the external device 6.

Information transfer controlling system

Abstract: PURPOSE:To increase the throughput of a channel and to reduce the access disturbance of the channel to a main memory by providing a memory controller containing two buffers among the main memory, a processor and the channel respectively. CONSTITUTION:Main memories MSU0-MSU3, central arithmetic processors CPU0 and CPU1 having cache memories CM and channels CHP0 and CHP1 are connected via the 1st and 2nd buffers GBS and CHB. The buffer GBS has a capacity larger than the cache memory CM of the CPU, and the buffer CHB is divided for each channel part. This system increases the throughput of the channel and reduces the access disturbance of the channel to the main memory. Thus the overall system performance can be improved.

Picture data transfer device

Abstract: PURPOSE:To obtain a data transfer device possible for display of picture data without losing the high speed operating function, by separating a picture processing memory and a display only memory at an address space. CONSTITUTION:An external memory 1 being an original picture, a processing picture, and a picture processing program area is accessible from any of a high speed operating section 8 and an address converter 5 managing the transfer of picture, the data read out from the external memory 1 is converted into a required bit length for display at a data converter 7 in the transfer mode and written in the display only memory 4. The end of transfer is discriminated with a vertical synchronizing signal VD from a CRT timing generator 3 by a frame memory controller 6, and a timing output Go is switched into the non-transfer mode. The high speed operation section 8 is operationable in the non-transfer mode, the operation processing of the original picture data is attained while accessing sequentially the picture processing program, and the picture after processing is stored sequentialy in the processing picture data storage area.

Control system of interruption

Abstract: PURPOSE:To reduce the load of a channel processor by executing an interruption after fetching the address information on an input/output device and the channel status word through a CPU itself and informing this execution of interruption to the channel processor. CONSTITUTION:The communication is possible through a memory controller 2 between CPU1-0- and a channel processor 4 which controls channel devices 5-0- respectively, and is possible to access independently to a main memory 3 via the controller 2. The memory 3 stores the address information on the input/ output device related to the input/output interruption, the channel status word and an interrupon control word 6. The CPU1-0- read independently both said address information and status word out of the memory 3 in response to the interruption request fed from the processor 4 and then executes the interruption processing. The information on this execution is informed to the processor 4 together with the end of execution of the interruption processing.