Showing papers on "Memory controller published in 1987"

Dual port memory controller

Abstract: A dual port memory controller is operative to interface a pair of processors to a common multiple bank organized memory. A dedicated logic array provides arbitration between conflicting processor requests for memory access. Refresh means are operative upon the memory banks in a staggered fashion to minimize noise created within the system during refresh and to permit simultaneous refresh of an access to the memory.

Memory control subsystem

Abstract: The memory control subsystem controls and arbitrates the access to a memory 10 which is shared by a plurality of users comprising at least a processor 2 with its cache and input/output devices 4 having direct access to the memory through a direct memory access bus 12. It comprises a processor controller 20, a DMA controller 22 and a memory controller 24. A processor request is buffered into the processor controller 20 and is serviced right away if the memory controller is available, possibly with a simulataneous transfer between the devices 4 and buffers in the DMA controller 22. If the memory controller 24 is busy, because a DMA request is being serviced, the DMA controller comprises means to cause the DMA transfer to be interrupted, the processor request to be serviced and the DMA transfer to be resumed afterwards. Write requests made by the processor are buffered into processor controller 20 and an acknowledgement signal is sent to the processor which can resume execution without waiting the memory update completion. A read request which does not hit the cache is sent to the processor controller which causes the cache to be updated. In case of multiple processor requests contending with a long DMA transfer, the latter is sliced into several parts, each part mapping one cache line. In case of a DMA write, the cache lines which correspond to memory positions whose content is modified by the write operation are invalidated in such a way that the processor cannot read a partially written line into the cache.

Memory cartridge having a multi-memory controller with memory bank switching capabilities and data processing apparatus

Abstract: A memory cartridge having a case and a printed circuit board housed in the case is connected, in use, to a data processing unit including a microprocessor and a picture processing unit. A memory cooperating with the data processing unit is installed on the printed circuit board, and an area of the memory is divided into a plurality of banks. A multi-memory controller installed on the printed circuit board includes a plurality of registers into which microprocessor generated data, representing bank switching conditions, are loaded. An address for switching the memory banks is output in response to the content of at least one of a plurality of registers. Thus, by changing the above-described data, the microprocessor can specify a specific bank at a specific time and utilize that bank.

Image frame buffer access speedup by providing multiple buffer controllers each containing command FIFO buffers

Abstract: A frame buffer memory controller allows rapid image updating while maintaining screen refresh data flow rate. One frame buffer memory controller controls one or more pixel depth columns comprising one or more frame buffer memory chips per pixel. Each frame buffer memory controller listens on a display processor bus for read, write or read-modify-write commands addressed to a pixel, or memory chip, under its control. Such commands, along with the associated addresses and data, are stored in a first-in, first-out (FIFO) buffer for execution during the first free memory cycle.

Semiconductor memory device with testing of redundant memory cells

Abstract: A semiconductor memory device includes a main memory cell array, a redundancy memory cell array, bonding pads for receiving an address signal, a row decoder for selecting a row of the main memory cell array in accordance with the row address signal, and an exchange controller connected to receive the address signal, which is programmable to inhibit the selective operation of the row decoder to select the row of the redundancy memory cell array, in response to specific address signals. The semiconductor memory device further includes bonding pads, each for receiving a test signal. The exchange controller is connected to receive the test signal for inhibiting the selective operation of the row decoder and selecting the row of the redundancy memory cell array, in response to the test signal.

Scan test apparatus for digital systems having dynamic random access memory

Abstract: A scan test apparatus is constructed to scan test a digital system having a memory system containing dynamic random access memory (DRAM). The scan test apparatus is given access to the memory system so that test control signals can preset the refresh counter (for the DRAM) and initialize the memory for later testing.

Memory controller for protected memory with automatic access granting capability

Abstract: A method and apparatus for controlling access to data blocks stored by addresses in a memory and concurrently accessible by a plurality of transactions is provided. The method includes the steps of receiving an address of a data block to be accessed by a first transaction, deriving from the address an access table entry corresponding to the data block where the entry includes lock data that governs access to the data block, and providing the access if permitted by the lock data, or providing the access, if not permitted by the lock data, and recording the occurrence of the access in the lock data.

Image generating system for duplex printing

Abstract: An image generation system includes a data processor for carrying out data processing operations along with a read only memory (ROM) and random access memory (RAM). A bus bar interconnects the various units to establish a flow of commands and data. A floppy disk controller operates as an interface for a floppy disk drive and a direct memory access controller controls the floppy disk controller for the transfer of data to the RAM. A serial communication controller serves as an interface between the flow of data from the image generation system to a printer engine. A bit-map means operates for storing, addressing and re-organizing data for normal and duplex printing.

Bus activity sequence controller

Abstract: The present invention relates to a computer system having a sequence controller for allowing direct memory access devices to access peripheral devices. The sequence controller allows the peripheral devices access to a global bus by providing access in a round-robin fashion. A microprocessor associated with the sequence controller and direct memory access has access to the global bus after each direct memory access. The amount of data allowed to be transferred in each direct memory access is restricted so that each device is equally serviced.

Work station dealing with image data

Abstract: A work station of a computer system capable of batch storing and retrieving image data separately from a usual data file system, equipped with a main processor, main processor memory and direct memory access (DMA) controller connected to a common bus, equipped with a graphic processor and window memory between the common bus and an image data bus, and equipped with a frame memory in connection with an image display unit on the image data bus, wherein the work station is further provided with an image data memory, e.g., disk unit, on the image data bus, a memory input/output controller lcoated between the image data memory and the image data bus for controlling image data transfer using a direct memory access (DMA) function, and an image data input unit and output unit connected to the memory input/output controller, so that mass image data can be transferred directly between the memory and input/output units under control of the memory input/output controller without going through the window memory.

System for reducing I/O controller overhead by using a peripheral controller for producing read, write, and address translation request signals

Abstract: In a data processing system which is for use in combination with at least one peripheral device and comprises an input-output processor connected to a first and a second bus, a main memory connected to the first bus, a peripheral controller connected to the second bus and the peripheral device, and a central processor connected to the first bus and coupled to the second bus through the input-output processor, the peripheral controller requests data transfer between the main memory and the peripheral device. For this purpose, the peripheral controller produces a translation request signal in response to a channel command which is stored in a local memory of the peripheral controller from the main memory through the input-output processor and indicates the data transfer. Receiving the translation request signal through the input-output processor, the central processor translates into a physical data address a logical data address which accompanies the channel command and is stored in the local memory from the main memory. On transferring data from the main memory to the peripheral device, the peripheral controller produces a read command signal in response to the physical data address received through the input-output processor. In a similar manner, the peripheral controller produces a write command signal on transferring data from the peripheral device to the main memory.

Multiple computer interface

Abstract: A multiple computer interface (10) for connecting a plurality of computers (28) in a network system. The interface (10) interconnects a plurality of computers or central processing units (28) to a main computer control arrangement, the arrangement comprising a management control central processing unit (16), main memory storage (31) and memory controller (24) for shared programs, as well as a main central processing unit controller (18) for peripheral I/O devices, such as printers (36).

Optical image transformation apparatus

Abstract: A plurality of photocells (1) are two-dimensionally arranged on a single light-image receiving plane. Each photocell (1) is connected to first and second sum signal output lines (2, 3). These lines (2, 3) receive output signals from the photocells (1) through transmission switches (4), and output sum signals of these signals to an amplifier (5). The amplifier (5) outputs a difference between the two signals received from the first and second sum signal output lines (2, 3). A memory (6) stores control signals including weighting data for controlling transmission, isolation, amplification factors, and/or attenuation factors with respect to the individual transmission switches (4), and outputs the control signals to the transmission switches (4). Each transmission switch (4) multiplies or does not multiply the output signal from the corresponding photocell (1) with a specific amplification or attenuation factor, and transmits the product to the first or second sum signal output line (2, 3). A memory controller (7) writes the weighting data into the memory (6). A function generator (8) outputs the weighting data of a two-­dimensional function.

Computer video control system

Abstract: Video control circuitry for controlling the video format presented to the cathode ray tube or screen and capable of providing a combination of character generation and cell generation along with other video types of control. The video controller may comprise a video memory means for controlling writing into and reading therefrom and means defining both a memory address and a memory data. There is a video data bus coupled to the video memory means and a processor address bus. A cathode ray tube controller has address lines and the address lines are connected to multiplexer means for selecting either the controller address lines or the processor lines. Control means are provided for controlling the multiplexer means so that in one state thereof the video memory means is addressed from the cathode ray tube controller means and in the other state the video memory means is addressed from the central processing unit address. This occurs on an interleaved basis with the CRT clock basically operating at the normal refresh cycle rate. However, in accordance with the invention the CRT clock is essentially divided so that one half of the clock cycle is used for communication from the CPU to the video memory means. This provides for improved screen display.

4Mbit DRAM design including 16-bit-concurrent ECC

Abstract: An alpha-induced soft error becomes serious problem with increase in scale of dynamic RAM's(DRAM's). In order to achieve higher reliability for a high density digital memory system, not only the structure of an alpha immunity memory cell but also on-chip ECC(Error Checking and Correction) circuit should be considered. This paper describes an on-chip ECC circuit which checks 16 bit data concurrently. The ECC circuit is applied to 4Mbit DRAM.

Dual port memory

Abstract: PURPOSE:To operate as a memory having a density converting processing function by an external command by adding a density converting processing circuit to a port memory. CONSTITUTION:An ordinary memory operation is carried out by transmitting an address, data and a read/write signal to a dual port memory controller 4 from the respective ports. When performing the density converting processing, the original dual pot memory functions as a simple input and output device. Accordingly, A CPU of the port A side designates a density converting processing command, a storage leading address to the memory 5 and the number of transfer data are designated. Thereby, in the operation thereafter, a LOW (I/O write) command is successively transmitted. On the density converting processing, the address, the read/write signal and the data are all transmitted from the density converting processing circuit 1 to the dual port memory controller 4.

Digital System Design: State Machine Versus Microprocessor Controller

Abstract: This paper considers the use of a microprocessor as a controller for digital systems. It is suggested that the microprocessor controller can be considered as a state machine with each state being defined in terms of possible machine instructions. The strengths and weaknesses of this device are discussed. A design procedure is proposed that allows comparison of a conventional state machine design to microprocessor design of a digital system that contains a sequential controller.

Semiconductor memory device carrying out a self-refresh operation

Abstract: A semiconductor memory device carries out a self-refresh operation in response to a refresh request signal. The device includes a memory cell array (12) formed on a chip (10); a plurality of pseudo memory cells (PMC₁ , PMC₂ , ---,) distributed and arranged on the chip, each having the same constitution as the memory cells in the memory cell array; a first circuit (Qa, Q₁ , Q₂ , ---, L₂ , L₃ , VCC) for monitoring the capacitor voltage in the pseudo memory cells; and a second circuit (16) for generating the refresh request signal (φRFSH) and charging each capacitor in the pseudo memory cells. When the potential of at least one of the capacitors in the pseudo cells falls below a predetermined level, the refresh request signal is generated, thereby enabling the device to lengthen a refresh interval and thereby decrease power dissipation, while facilitating adjustment work.

Convergence error correction method

Abstract: PURPOSE:To improve the accuracy and speed of error correction by using a signal of low frequency as an error detection pattern to reduce the effect of noise or jitter in a display device such as a color picture tube. CONSTITUTION:A signal generator 2 forms a low-frequency signal, and for example, as shown in a figure, a signal having a repetitive pattern in both horizontal axis (x) and vertical direction axis (y) of the pattern is generated. A video signal from an image pickup device 4 is led first to a synchronizing separator circuit 8 in a picture processor 5, converted into a digital signal by an A/D converter 7 and fed to a picture memory 9. Then a memory controller 10 is operated by using a synchronizing signal formed by a synchronizing separator circuit 8 and the video signal is stored in the picture memory 9 so as to be proessed easily by a computer 11. The signal is picked up by the device 4 and inputted to the memory 9 in the unit 5. Actually, in executing the computer simulation, even when division numbers N1,M1 are nearly 10, the error of nearly l/10 of one scanning line of the image pickup device 4 is detected.

Memory control system

Abstract: PURPOSE:To improve the processing capacity of a memory control system by attaining an access even to a main memory area which is locked by another device and sending back an answer signal showing an under-lock state. CONSTITUTION:A main memory device 1 is shared by one or more instruction processors 2 and one or more input/output processors 3. A main memory controller 4 controls the access to the device 1 through both processors 2 and 3. When an access request is given to the area of the device 1 locked by another device, the access is started to the device 1 regardless of a locked or unlocked state of said access request. Then the answer signal given from the device 1 is sent back to the access requester. The access requester discriminates that the device 1 is kept under a locked state and decides to wait until the lock is released or to perform another job.

Bit map memory controller

Abstract: PURPOSE:To facilitate LSI-implementation without increasing the data bus width of a component by providing a means which mixing the 1st circulation data and the 2nd circulation data which data in addresses including a destination area CONSTITUTION:Barrel shifters 5-1 and 5-2 rotate input data under the control of a control circuit which is not shown in a figure according to the dot address value of a destination Further, ALUs 7-1 and 7-2 performs logical operation among corresponding bits of input data of three systems Then, a composing circuit 20 mixes the outputs of the ALUs 7-1 and 7-2 according to the value the readout head address of the destination to generate 32-bit data Further, 32-bit data are arranged to 64 bits and 64-bit data is composed of 64-bit data read out of bit map memories 1-1-1-4 and outputted to the memories 1-1-1-4

Waveform memory controller

Abstract: PURPOSE:To improve a measuring efficiency by prohibiting a waveform updating processing after the time when input signals after the second one are out of a discrimination region. CONSTITUTION:When newly sampled waveform data are transferred from a sampling data memory 6 to a display memory 8 in order to update the memory 8 by the newly sampled waveform data when reference signals are observed, the newly sampled waveform data are also transferred to an upper and lower limit value calculating circuit 11. The circuit 11 performs the setting processing of a discrimination region by sequentially storing upper or lower limit value data obtained by using the newly sampled waveform data in an upper or a lower limit value memory 12 or 13, respectively. In comparing the data V from the memory 6 with the data VH or VL from the memory 12 or 13, only when a V>VH or V

Line condition data collecting system for a telephone exchange

Abstract: A line condition data collecting system for a telephone exchange includes an image memory (8) in a central processing unit (1) which stores line condition data to reduce the amount of time central controller (11) in the central processing unit (1) waits for the line condition data. A signal receiving memory in the telephone exchange stores the line condition data and is sequentially accessed by an image memory controller (9) autonomously from the central controller (11) in the central processing unit (1). When the central controller (11) requires line condition data, the image memory (8) is checked and if the line condition data stored therein is valid, it is supplied to the central controller (11). If the line condition data in the image memory (8) is invalid, a conventional access request is made to the signal receiving memory, but this occurs less frequently than in a conventional system.

Communication system between microprocessor and memory or peripheral lsi

Abstract: PURPOSE:To make encipherment of a data between a processor and a memory to be secured by using an access area identification means provided to a microprocessor chip so as to identify a designation area via an address bus and selecting a route via a cryptographic/decoding circuit. CONSTITUTION:Based on an address via an address bus, an access area identification means of a microprocessor chip 10 identifies whether an access area is a peripheral LSI 3 or a memory 2. In case of the memory 2 as the result of identification, a switch is changed over, an encipherment/decode circuit 5 is interposed between the microprocessor 1 and the memory 2 to form a route. As a result, the data between the microprocessor and the memory is made encipherment to secure the data in an excellent way.

Nanosequencer digital logic controller

Abstract: A digital logic controller providing instruction execution times on the order of 50 nanoseconds and employing a read-only memory outputting instructions to a pipeline register, a portion of each instruction providing a status-select control signal and address signals for controlling selection of the next instruction from the read-only memory.

Diagnosis control system for information processor

Abstract: PURPOSE:To offer an easy maintenance system to the maintenance operator of an information processor by reading the result of the self-diagnosis held by each controller via an exclusive diagnosis bus and then displaying an abnor mal package to be replaced. CONSTITUTION:A central processing unit 11, a memory controller 12, and input/ output controllers 13 and 14 carry out the self-diagnosis jobs respectively when a power supply is applied with an information processor or when the system initialization is carried out by the unit 11. The results of said self-diagnosis jobs are held by each state register. When a diagnosing device 17 carries out a command to each controller, these controllers send the results of their diagnosis held by each state register to the device 17 via a diagnosis bus 19. The device 17 stores the package names of all controllers and checks the correspondence to each package with input of the result of diagnosis. Then the device 17 displays the data on a defective package on a diagnosis display device 18.

Data processing device for use in scintillation camera apparatus

Abstract: A scintillation camera apparatus adapted for displaying an image representing a radioisotope distribution within a subject under examination at a substantially constant level in image density during a persistent data acquisition procedure comprises an auxiliary memory for sequentially storing position signals representing detected positions of gamma rays, and an image memory for storing a count representing the frequency of detection of gamma rays in a memory location accessed by position signals. The auxiliary memory has a predetermined capacity, and thus, when the number of the sequentially stored position signals exceeds this memory capacity, the earliest-entered position signals stored therein are made to overflow therefrom. A memory controller accesses a location in the image memory by means of the overflowed position signals and decrements the content at the accessed location. After position signals are made to overflow from the auxiliary memory, the quantity of data stored in the image memory (the total number of counts of gamma rays) remains always at a constant value equal to the capacity of the auxiliary memory.