Showing papers on "Memory management published in 1971"

The Organization and Use of Parallel Memories

Abstract: As computer CPUs get faster, primary memories tend to be organized in parallel banks. The fastest machines now being developed can fetch of the order of 100 words in parallel. Unless memory and compiler designers are careful, serious memory conflicts and resulting performance degradation may result. Some of the important questions of design and use of such memories are discussed.

Program restructuring for virtual memory

Abstract: Program reference patterns can have a more profound effect on paging performance in a virtual memory system than page replacement algorithms. This paper describes experimental techniques that can significantly reduce paging exceptions in existing, frequently executed programs. Automated procedures reorder relocatable program sectors, and computer displays of memory usage facilitate further optimization of program structure.

A net structure for semantic information storage, deducation and retrieval

Abstract: This paper describes a data structure, MENS (MEmory Net Structure), that is useful for storing semantic information stemming from a natural language, and a system, MENTAL (MEmory Net That Answers and Learns) that interacts with a user (human or program), stores information into and retrieves information from MENS and interprets some information in MENS as rules telling it how to deduce new information from what is already stored. MENTAL can be used as a guestion-answering system with formatted input /output, as a vehicle for experimenting with various theories of semantic structures or as the memory management portion of a natural language question-answering system.

Memory protection system providing fixed, conditional and free memory portions corresponding to ranges of memory address numbers

Abstract: A method and apparatus for flexible protection against overwriting and destruction of the contents of selected portions of a computer memory device formed of a multiplicity of memory units. Each memory unit is assigned a unique memory address number which serves to identify the memory unit in instructions to write data into the memory. The address numbers are segregated into ranges of numbers defining separate memory portions to be protected, with the numbers at the limits or boundaries of the ranges being entered in registers which can be reset to flexibly determine the protected ranges. The memory device is separated in this fashion into three different portions: one permitting free writing access to the memory units, one withholding all writing access to the memory units, and one being conditioned to grant or withhold writing access according to the setting of a device such as flip-flop which can be arranged for manual or programable control. Whenever an instruction to alter a memory unit arises, the associated address number is entered in a register and compared by means of digital comparators with the range boundary numbers in their registers. Gate means grant or withhold access to the memory unit in accordance with the comparison, thereby controlling the insertion of data into each memory unit and providing protection for selected portions of the memory device.

On modeling program behavior

Abstract: This is a paper about the history of the working set model for program behavior. It traces briefly the origins and bases of the idea and some of the results subsequently obtained. The physical context is a hierarchical memory system consisting of a severely limited quantity of main (directly-addressable) storage and an essentially unlimited quantity of secondary (backup) storage. In this context, the intuitive notion of "working information" as the set of words which are (or should be) loaded in main memory at any given time in order that a program may operate efficiently is as old as programming itself. The sharply increased interest in program models since the mid-1960s is a direct consequence of the widening use of virtual memory and multiprogramming techniques, which have shifted the responsibility of memory management from programmers to machines. I am assuming here that the purpose of memory management is ensuring that an active program's working information is present in main memory, and the purpose of a program model is providing a basis for determining a program's working information at a given time and predicting what it will be at a future time.

System for controlling power consumption in a computer

Abstract: The disclosed system causes power to be removed from the memory for a chosen time duration after each time that the memory is used. The time duration can be chosen as desired and is specified by a ''''WAIT N'''' instruction. When this instruction appears, the power to the memory is removed therefrom and accesses to the memory are prevented. The time duration is entered into a register and the contents of this register are compared with the contents of a counter which has a clock pulse train applied thereto until equality is attained whereby an equality signal issues. The latter signal is applied to restore power to the memory and, with appropriate logic, permits accesses to the memory, read or write, for example. When the memory accessing is completed, the N units specified by the ''''WAIT N'''' instruction would be usable at the option of the program to control access to the memory and to remove power therefrom for the duration of N time units. A new ''''WAIT N'''' instruction can change the time duration.

Apparatus and method for memory refreshment control

Abstract: Apparatus and method for controlling the refreshing of volatile memory elements associated with data processing units. The invention minimizes the conflict between the memory refresh operation and the requirements for access to the memory elements during data processing operations. When conflict is unavoidable, it is resolved in favor of the refresh cycle to prevent loss of information. In memory elements of the type which are automatically refreshed during utilization by the data processing unit, a separate refresh cycle is eliminated when the utilization takes place in an appropriate interval.

A stored program controlled electronic communication switching system

Abstract: A stored program controlled electronic communication switching system provided with central control units having access to a memory consisting of high speed memory devices and low speed memory devices, such as magnetic drums. The low speed devices cooperate with said high speed devices so that data can be transferred therebetween to reduce the cost ratio of the memory necessary to meet the service specification of the system. The system further comprises means for minimizing the access time to the low speed memory devices. The central control units and the low speed memory devices are of duplicated construction in order to provide high reliability. Furthermore facilities are provided to enable the system to operate in a fallback mode, should faults occur, by changing the allocation of the content of memories to thereby modify the processing mode of the system without altering the processing program itself.

Optimal sizing, loading and re-loading in a multi-level memory hierarchy system

Abstract: Starting with the appearance of the third generation computers the demand for memory storage devices has increased. This increased demand has been for both the main storage and auxiliary storage devices. The major reasons for this increase were the problems of larger data processing tasks and the introduction of multiprogramming and time-sharing.

Digital computer having a plurality of serial storage devices for central memory

Abstract: A small digital computer is described having a unique memory configuration which makes the computer quite suitable for highly interactive uses and yet places it in a price range similar to that of an electric desk calculator. The computer includes an input keyboard arrangement enabling an operator to directly deliver data to the computer, as well as a processor for manipulating data. The central memory is made up of four magnetostrictive delay lines, and secondary storage is provided in the form of a tape cassette. The control unit for directing operation of the computer is adapted to transfer data between one of the delay lines of central memory and the secondary storage at the same time data is being directed between another one of the storage devices and the processor for manipulation.

Program control unit for a digital data processing installation

Abstract: A program control unit for a digital data processing installation is described. The program control delivers macro-commands from a macro-command memory, and micro-commands from a micro-command memory. The micro-commands can be delivered singly or in selected combinations. In addition to the main commands in the macro-command memory which act as macro-commands for directly releasing micro-programs, there are also main commands which follow each other and indirectly cause the delivery of one or more micro-commands. Indirect delivery of micro-commands is caused in any case by a machine address of a memory cell, belonging to the pertinent main command, related to the macro-command memory for another macro-command. At least one auxiliary command which can be called up by different main commands is contained in a memory cell of this type. Each auxiliary command determines, by means of a micro-command machine address related thereto of the memory cell in the micro-command memory, the delivery of this micro-command or the delivery of this micro-command and the micro-command which follows in the micro-command memory.

The physical attributes and testing aspects of the symbol system

Abstract: The major goals of the SYMBOL computer research project have been to provide a more effective man-machine interface and to reduce the total cost of a digital system to the user. The development of the multi-processing/multi-programming computer architecture with much of the executive system, memory management, and high-level language implemented in hardware is described in other related papers. The SYMBOL project also has investigated low-cost construction techniques suitable for equipment to be used in commercial/industrial environments.

Storage utilization in a memory hierarchy when storage assignment is performed by a hashing algorithm

Abstract: The utilization of storage is studied in a two-level memory hierarchy. The first storage level, which is the fast store, is divided into a number of storage areas. When an entry is to be filed in the hierarchy, a hashing algorithm will attempt to place the entry into one of these areas. If this particular area is full, then the entry will be placed into the slower second-level store, even though other areas in the first-level store may have space available. Given that N entries have been filed in the entire hierarchy, an expression is derived for the expected number of entries filed in the first-level store. This expression gives a measure of how effectively the first-level store is being used. By means of examples, storage utilization is then studied as a function of the hashing algorithm, the number of storage areas into which the first-level store is divided and the total size of the first-level store.

Experiments in page activity determination

Abstract: In a memory hierarchy various storage devices are structured into various levels. By convention, information at storage level i may be accessed and stored in less time than information at storage level i+1. Since a smaller access time generally implies a greater cost per bit of storage, storage level i will generally be smaller than storage level i+1. An example of such an arrangement with four levels is a system with core, drum, disc and tape memory devices.

Homogeneous memory for digital computer systems

Abstract: A digital computer system with a memory unit comprising both ''''read-only'''' locations from which information can only be read and ''''read-write'''' locations from which information can be read and into which information can be written. Both read-only and read-write memory locations store information in the same format, but each read-only location contains an extra bit position for a ''''state'''' bit. The digital computer system normally addresses the read-only locations in sequence. If a state bit in any read-only location is set, a control in the memory interprets the information in that location as an address, normally for a readwrite memory location for storage or retrieval of information. When the state bit is not set, the read-only location contains information for direct use by the digital computer system.

Priority paging algorithms and the extension problem

Abstract: Given a particular computer system the extension problem concerns the prediction of performance when the size of main memory is increased. In this paper a specific approach to this problem is formulated for demand paging systems. A necessary and sufficient condition on the nature of page replacement rules which leads to solutions of the extension problem is a major result of the paper. As the other principal result we show that the class of replacement rules so defined is precisely that class of rules having the wellknown inclusion property. The paper concludes with a general discussion of topics related to the extension problem.