Showing papers on "Memory management published in 1977"

Cm*: a modular, multi-microprocessor

Abstract: This paper describes the architecture of a new large multi-processor computer system being built at Carnegie-Mellon University. The system allows close cooperation between large numbers of inexpensive processors. All processors share access to a single virtual memory address space. There are no arbitrary limits on the number of processors, amount of memory or communication bandwidth in the system. Considerable support is provided for low level operating system primitives and inter-process communication.

The Multidimensional Access Memory in STARAN

Abstract: STARAN® has a number of array modules, each with a multidimensional access (MDA) memory. The implementation of this memory with random-access memory (RAM) chips is described. Because data can be accessed in either the word direction or the bit-slice direction, associative processing is possible without the need for costly, custom-made logic-in-memory chips.

Memory clear system

Abstract: A memory clear method useful to clear a plurality of words contained in a memory from a specific address to an address at the same time. An address register is provided for this purpose. In one preferred form, the address register is responsive to a CX key indicating a memory clear operation, a , key indicating start of the memory clear operation and 0 to 9 digit keys identifying a memory address for the memory clear operation.

On the Effective Bandwidth of Parallel Memories

Abstract: The object of this paper is to bring together several models of interleaved or parallel memory systems and to expose some of the underlying assumptions about the address streams in each model. We derive the performance for each model, either analytically or by simulation, and discuss why it yields better or worse performance than other models (e.g., because of dependencies in the address stream or hardware queues, etc.). We also show that the performance of a properly designed system can be a linear rather than a square root function of the number of memories and processors.

Two Methods for the Efficient Analysis of Memory Address Trace Data

Abstract: The high cost of analyzing long memory address traces has limited most researchers to short traces and analysis algorithms that are linear in the length of the trace. We suggest two methods that permit a trace to be shortened in length by one to two orders of magnitude (or more) for later further analysis. The Stack Deletion Method eliminates all references in the trace to the top k levels of the LRU stack. The Snapshot Method records the reference bits of the pages in the original tape at discrete intervals and uses these bits to generate a new trace. Extensive measurements are presented, from which we conclude that there is little or no loss in accuracy using reduced traces for many purposes for a wide range of memory sizes and degrees of reduction.

A comparison of next-fit, first-fit, and best-fit

Abstract: “Next-fit” allocation differs from first-fit in that a first-fit allocator commences its search for free space at a fixed end of memory, whereas a next-fit allocator commences its search wherever it previously stopped searching. This strategy is called “modified first-fit” by Shore [2] and is significantly faster than the first-fit allocator. To evaluate the relative efficiency of next-fit (as well as to confirm Shore's results) a simulation was written in Basic Plus on the PDP-11, using doubly linked lists to emulate the memory structure of the simulated computer. The simulation was designed to perform essentially in the manner described in [2]. The results of the simulation of the three methods show that the efficiency of next-fit is decidedly inferior to first-fit and best-fit when the mean size of the block requested is less than about 1/16 the total memory available. Beyond this point all three allocation schemes have similar efficiencies.

Information content of CPU memory referencing behavior

Abstract: The memory reference trace of a computation is modeled as a probabilistic process and the information content of that process is derived. Techniques are developed for analyzing the effectiveness of the addressing architecture and Memory/CPU traffic of existing machines with respect to the information theoretic bound for a given trace.Several techniques for analyzing particular aspects of addressing architecture are also developed. Possible areas of improvement for addressing architecture, compilers, and memory architecture are suggested for performance enhancement.

Organization of Semiconductor Memories for Parallel-Pipelined Processors

Abstract: An organization of interleaved multimodule semiconductor memories is studied to facilitate accessing of memory words by a parallel-pipelined processor. All modules are assumed to be identical and to have address cycle (address hold time) and memory cycle of a and c segment time units, respectively. A total of N(=2n) memory modules are arranged such that there are l(=2b) lines for addresses and m(=2n-b) memory modules per line. For a parallel-pipelined processor of order (s,p) which consists of P parallel processors each of which has s degrees of multiprogramming, there can be up to s · p memory requests in each instruction cycle. Memory request collisions are bound to occur in such a system. Performance is evaluated as a function of the memory configuration. Results show that for reasonably large values of N, high performance can be obtained even in the nonbuffered case when l is a · p or more. Buffering has maximum effect on performance when l is near a · p. When l must be grater than a · p for adequate performance in the nonbuffered case, buffering can be used to reduce l while maintaining performance.

Memory management and response time

Abstract: This paper presents a computationally tractable methodology for including accurately the effects of finite memory size and workload memory requirements in queueing network models of computer systems. Empirical analyses and analytic studies based on applying this methodology to an actual multiaccess interactive system are reported. Relations between workload variables such as memory requirement distribution and job swap time, and performance measures such as response time and memory utilization are graphically displayed. A multiphase, analytically soluble model is proposed as being broadly applicable to the analysis of interactive computer systems which use nonpaged memories.

Secondary storage facility for connecting to a digital data processing system by separate control information and data transfer paths

Abstract: A secondary storage facility that connects to a digital data processing system. The system includes a central processor, an associative memory and a random access memory connected to the associative memory. The secondary storage facility includes a controller and one or more direct access secondary storage units. A first bus connector interconnects the controller to a first bus from the central processor and transfers of control information are routed over this bus. The controller also connects to the associative memory so that data, together with address and control information, is routed between the random access memory and a storage unit through this second connection.

Dynamic memory allocation in computer simulation

Abstract: e of 35 dynamic memory allocation algorithms when used to service simulation programs as represented by 18 test cases. Algorithm performance was measured in terms of processing time, memory usage, and external memory fragmentation. Algorithms maintaining separate free space lists for each size of memory block used tended to perform quite well compared with other algorithms. Simple algorithms operating on memory ordered lists (without any free list) performed surprisingly well. Algorithms employing power-of-two block sizes had favorable processing requirements but generally unfavorable memory usage. Algorithms employing LIFO, FIFO, or memory ordered free lists generally performed poorly compared with others.

Interrupt request controller for data processing system

Abstract: A memory control processor adapted to expand a random access or accelerator memory by logical overlays which performs these overlays into memory fields (pages) on the basis of page usage history. To provide a quick reference to page use a chronological sequence is established by links rather than by reordering a stack. This link sequence is tied by very limited leads to the rest of the memory control processor and can therefore be updated during each memory access. In addition the memory control processor includes a task priority logic integrating various competing memory access requests with the overlay operations. To achieve the various transfer modes in the quickest time the memory control processor is organized around a wide control memory storing the task servicing sequences. The width of the control memory and the associated task logic allow general purpose microprogrammable direct memory access which may further be utilized in multiplexed fashion to accommodate various concurrent tasks.

On a Varistructured Array of Microprocessors

Abstract: The varistructure architecture gives the user the opportunity to specify the height and width of his primary memory ``at run time.'' This architecture, first proposed in 1973, has now been simplified to make it schedulable, extended to allow SIMD vector-vector operations, and further extended to provide variable structure within a task. Memory is efficiently utilized in that memory bandwidth can be increased for array processing, yet memory space is not wasted during string processing. The fetch-execute cycle operation is analyzed herein, and some tentative results regarding input-output and data communication between processing entities are reported. On the basis of the simplicity of the fetch-execute cycle, there is hope that this architecture may well be the best way to build minicomputers and large computers using a cellular array of microprocessors.

Multiprocessor memory organization and memory interference

Abstract: ture of shared memory in a multiprocessor computer system is examined with particular attention to noninterleaved memory. Alternative memory organizations are compared and it is shown that a home memory organization, in which each processor is associated with one or more memories in which its address space is concentrated, is quite effective in reducing memory interference. Home memory organization is shown to be particularly suited to certain specialized computational problems as well as to possess advantages in terms of interference and reliability for general purpose computation. Results for interleaved memory are drawn from previous work and are used for comparison. Trace-driven simulations are used to verify the conclusions of the analysis.

Hierarchially arranged memory system for a data processing arrangement having virtual addressing

Abstract: A hierarchially arranged memory system is described for a data processing system having virtual addressing. A three-level working memory is provided, along with an auxiliary memory, in a data processing system containing a secondary buffer between the main memory and a rapid buffer memory. Whereas the main memory contains all actual storage areas, i.e. the memory pages of the inactive processes which were required for the processing period just passed, the actual storage area for the successor process, independent from the operating system, is set independently by its own microprocessor.

A Shared Random Access Memory Resource for Multiprocessor Real-Time Systems

Abstract: A shared random-access memory resource is described which is used within real-time data acquisition and control systems with multiprocessor and multibus organizations. Hardware and software aspects are discussed in a specific example where interconnections are done via a UNIBUS. The general applicability of the approach is also discussed.

Reduction of memory interference in multiprocessor systems

Abstract: This paper reports results of a study to determine and compare the effectiveness of various techniques aimed at reducing memory interference in multiprocessor multi memory systems. A simulation model of a multiprocessor, driven by address traces, is used for evaluation purposes. Two approaches to interference reduction are considered, being the reduction of overlapping memory requirements through various memory allocation methods, and the use of local memory to reduce the request rate to shared memory. Both private and cache memory are considered for this purpose.

Some Performance Issues in Multiprocessor System Design

Abstract: Analytic and simulation models of memory interference have been reported in the literature. These models provide tools for analyzing various system architecture alternatives. Some of the design parameters are processor speed, memory speed, number of processors, number of memories, use of cache memories, high-order versus low-order interleaving, and memory allocation. This correspondence applies existing analytic and simulation models to the multiprocessor design space and presents guidelines for the multiprocessor system architect. Preferred design alternatives and tradeoffs are outlined.

A set of strategy-independent restructuring algorithms

Abstract: This paper proposes a set of new program restructuring algorithms which can be used to reorganize programs so as to increase their performance under two typical memory management strategies. The new algorithms are based on a recently proposed program behaviour model called the bounded locality intervals model, which allows us to give a precise definition of the localities of a program. The paging activities of a program restructured with the new algorithms under working-set and global LRU-like memory management strategies are simulated to evaluate the new algorithms. Some of them are shown to have quite satisfactory performance.

Time-division control system of refresh memory

Abstract: PURPOSE:To shorten a memory access time by causing access to that memory three times within a two-character display time.

Tertiary memory access and performance in the datacomputer

Abstract: The Datacomputer is a data base management system, developed by Computer Corporation of America, and designed for shared remote access to large on-line data sets. It makes use of tertiary memory which is large capacity slower access memory beyond primary core and secondary disk memory. The Datacomputer is the only operational general purpose system capable of efficiently handling data sets of over a trillion bits. A Datacomputer is currently operational on the Arpanet using the first public installation of the Ampex Tera Bit Memory as its tertiary mass storage sub-system. This paper is in the nature of a VLDB case study with particular attention to the mass storage device used, the tertiary memory access strategies used, and the features provided in the Datacomputer for handling very large data bases.

A collection of papers on Cm* : a multi-microprocessor computer system

Abstract: : This paper describes the architecture of a new large multiprocessor computer system being built at Carnegie-Mellon University. The system allows close cooperation between large numbers of inexpensive processors. All processors share access to a single virtual memory address space. There are no arbitrary limits on the number of processors, amount of memory or communication bandwidth in the system. Considerable support is provided for low level operating system primitives and inter-process communication. (Author)

A Command Language Based Data-Acquisition and Analysis System for Low Energy Physics

Abstract: An open-ended Command Language based data-acquisition and analysis system for low energy nuclear physics applications is described. The system is designed to accommodate user-written command functions as well as standard system functions. The system insulates users from each other so that a user has access to only his particular functions and those of the system. Features include a "Help" function, free format input with prompting for omitted parameters, an extensive error message facility, and dynamic memory management. Particular effort has been directed at making the system as natural and logical as possible to the physicist/user while giving him maximum flexibility in controlling his experiment. The incorporation of reasonable defaults, free format input, and extensive checking of input with appropriate diagnostics is essential. Although this paper details a system developed for nuclear physics applications, the techniques are applicable to a variety of data acquisition and control applications.

Hardware estimation of a process' primary memory requirements

Abstract: A minor hardware extension the Honeywell 6180 processor is demonstrated to allow the primary memory requirements of a process in Multics to be approximated. The additional hardware required for this estimate to be computed consists of a program accessible register containing the miss rate of the associative memory used for page table words. This primary memory requirement estimate was employed in an experimental version of Multics to control the level of multiprogramming in the system and to bill for memory usage. The resulting system's tuning parameters display configuration insensitivity, and it is conjectured that the system would also track shifts in the referencing characteristics of its workload and keep the system in tune.

Data management requirements: The similarity of memory management, database systems, and message processing

Abstract: Memory management, database management, and message processing have in the past been defined in a relatively narrow way. With memory management the problem was to obtain cost effective use of real memory. Given a multiprogrammed environment, virtual memory systems allowed more effective use of expensive real memory. Memory management has become even more important with the development of very large and complex memory hierarchies. Database management systems were developed to allow the more effective use, sharing, and control of data resources - objectives which operating systems had previously provided for hardware resources. The driving force behind message processing has been the increased use of data communications and computer networks. This paper will consider the basis of the overlap in these areas, their common data management functions. Data management, as defined in this paper, includes the locating, routing, moving, and translating of data resources and the locating, reserving, and releasing of physical resources, i.e., primary and secondary storage.The analysis performed in this paper is essential because of trends in computer architecture discussed below. Early hardware was designed for general purpose environments with software used to tailor it to specific applications. However, according to Gagliardi9 future systems will consist of a set of subsystems, including a storage subsystem at the core surrounded by computational, spooling, and communications subsystems. The computational subsystem is the traditional “number cruncher” part of the system. The spooling subsystem provides the I/O interface between the system and the outside world. The communications subsystem links the various subsystems together and provides an interface to the rest of the network if the system is part of a larger distributed system. The storage subsystem consists of all the system's storage resources and their control processes. It controls all levels of the system memory and storage hierarchy. The storage subsystem controls the allocation of the physical storage resources and the movement of the data resources through the system. Depending on how these resources are used, they may be non-conserved or conserved, and if conserved, either serially reusable or sharable. Physical and data resources may be located, and if necessary reserved, independently or jointly.

Control system for memory device

Abstract: PURPOSE:To minimize the deterioration of the using efficiency for the memory through refreshing by having a simultaneous execution of both the access request and the refresh request to the static memory part when a refresh request exists.

Local Memory for a High-Speed Digital Test System

Abstract: The choice of RAM or SR memory as local memory dictates many of the characteristics of a high-speed digital test system. This paper examines the impact of the choice on test program efficiency, test speed, and system cost. Understanding this impact is important to anyone testing PC boards containing dynamic LSI devices, such as microprocessors.

Effect of program localities on memory management strategies

Abstract: Programs tend to reference pages unequally and cluster references to certain pages in short time intervals. These properties depend on the tendency of program locality references and program phase transitions. The significant effects on system performances arise from the phase transition behavior. However, the phase transition behavior of programs has been rarely taken into account in the analysis of memory management strategies. This paper investigates the effect of the phase transition behavior on the total system performance. For this purpose, an elaborate simulation model of the multiprogrammed memory management has been developed for a time-sharing environment. The working set strategy and the local LRU strategy are modeled in the simulation system. A simple phase transition model and the simple LRU stack model are used as a program paging behavior model. Both cases are analyzed where (1) locality variations exist and phase transitions occur, and (2) only locality variations exist and phase transitions do not occur. The relations between the phase transition rate and the system performance are found in the above memory management strategies.

Dynamic memory allocation in a virtual memory computer.

Abstract: : A virtual memory is a hierarchial or multi-level memory with an address mapping mechanism and an allocation algorithm. The first level of the hierarchy is the primary memory. The primary memory has the highest speed and smallest capacity in the hierarchy. Subsequent levels have decreasing speed and increasing storage capacity. The addressing mechanism maps a program's address space into the physical memory space. The address space of the program can be much larger than the available capacity of the primary memory. For this thesis, a page-oriented addressing mechanism was employed. A page is a fixed size block of computer words associated with contiguous memory addresses. The allocation algorithm manages the flow of pages to and from the primary memory.