Showing papers on "Memory management published in 1979"

DBC—A Database Computer for Very Large Databases

Abstract: Design considerations of a database computer are presented in this paper. The overall architecture of the computer as well as the organization of its individual components are discussed. Several key concepts which are vital to database management are incorporated in the design and organization of the components. The concepts of tracks-in-parallel read-out and logic-per-some-track processing are provided in an on-line database store for the purpose of achieving high-volume content-addressability. The use of auxiliary information about the database for access precision and control has resulted in the design of a structure memory, an array of content-addressable memory and processor pairs, for large collections of indices. The choice of technologies for the implementation of these components is considered in terms of their cost and performance. Modified moving-head disk technology is chosen in order to support the very large on-line database store. Emerging technologies such as magnetic bubbles and CCD's are chosen for the structure memory on the basis of their matching performance with the on-line database store and their capability for parallel-in-blocks-and-serial-within-block processing. Five other important components are also disdissed in the paper. Their role in the database computer and relationship with the structure memory and on-line database store are delineated.

Solid State: VLSI: Some fundamental challenges: Defining and designing the products made possible by very-large-scale integration are first on the list of priority tasks

Abstract: A tremendous interest in VLSI is all around us. There is much talk of electron-beam and X-ray lithography tools to achieve VLSI's submicron structures. In all of the discussions, the implication is that VLSI will allow us to enjoy the same kind of fantastic low-cost advantages that previous IC technologies have provided in electronic products. Perhaps. But if the semiconductor industry had today a commercial million-transistor technology like VLSI, I'm not so sure it would know what to do with it. Besides products containing memory devices, it isn't clear how future VLSI can be used in electronic products.

A Multicomputer System with Dynamic Architecture

Abstract: This paper considers the organization of certain multicomputer systems with a particular type of dynamic architecture. The system allows one to reconfigure via software available hardware resources (widths of processors, memories, and I/O units), forming computers with different word sizes. A multicomputer system is formed from identical dynamic computer groups. Each group may assume a variety of architectural states which are distinct from each other by the number and sizes of concurrent computers. To construct one dynamic computer group, one uses a universal building module, an 8-bit microprocessor on an LSI chip, and standard memory units. This paper considers basic principles of dynamic computer group implementation: organization of parallel (for words) and serial (for instructions) exchange between primary memory and processor, automatic variation of the time intervals assigned for operations which are executed in differently sized computers, formation of the processor with variable word size, switching from one architectural state to another, scheduling of the memory, and task synchronization.

On the Analysis of Memory Conflicts and Bus Contentions in a Multiple-Microprocessor System

Abstract: This paper studies one of the most difficult and important problems in the design of cost-effective multiple-microprocessor systems. The combined effect of interference due to bus contentions and that due to memory conflicts is investigated. Reference models are defined and applied to obtain analytic results which can prove to be valuable tools in the design of multiple-microprocessor systems for time-critical control processes. The effect of memory mapping is also investigated and an algorithm is developed to obtain a mapping which can be used to minimize memory conflicts.

Program Behavior and the Performance of Interleaved Memories

Abstract: One of the major factors influencing the performance of an interleaved memory system is the behavior of the request sequence, but this is normally ignored. This paper examines this issue. Using trace driven simulations it is shown that the commonly used assumption, that each request is independently and equally likely to be to any module, is not valid. The duality of memory interference with paging behavior is noted and this suggests the use of the least-recently used stack model to model program behavior. Simulations indicate that this model is reasonably accurate. An accurate, though approximate, expression for the bandwidth is derived based upon this model.

Autonomous data communications subsystem

Abstract: A data communication subsystem for operation with a main host computer, the subsystem involving a plurality of Front-End Controllers (each of which handles data transfers for a particular type of peripheral terminal and type of transmission line), a Data Communication Processor which controls the activity of the Front-End Controllers, a local "autonomous" memory (sometimes called data communications memory) dedicated to storing instructions, control data, and information data primarily for data transfer operations, and a Basic Control Interface unit which ties together the autonomous memory, the Data Communications Processor, and the Front-End Controllers. The data communication subsystem includes means for sensing a halt or failure in the main host system and then operating in an "autonomous" mode to continuously provide for data transfer operations independent of the main system condition. The data communication subsystem also provides means for storage of data (tanking) on disk files when the main system is halted. Such disk storage also alleviates memory space requirements for the main memory and the local autonomous memory. The concept of "data communications memory" is applied as a memory space dedicated for data transfer operations. This memory space called "data communications memory" may be made to reside in host system main memory, a local autonomous memory, or even in internal memory space within the Data Communications Processor. However, on halt of the main host computer system, the local autonomous memory will operate as the data communications memory directly available to the data communication subsystem and will work independently of a halt in the main host computer system.

Memory preservation and verification system

Abstract: A memory preservation and verification system is provided in which memory contents are verified as being valid following an interruption and subsequent reapplication of operating power. A backup power supply is provided to maintain the status of the memory contents during the interruption or loss of a main power supply. First and second mathematically related numbers are generated and stored in memory locations. These numbers are subsequently retrieved and the mathematical relationship therebetween checked to provide the verification of the status of data in the memory.

Dynamic file assignment in a computer network--Part II: Decentralized control

Abstract: Optimal decentralized control of file assignment in computer networks is studied. We consider two types of information patterns: one-step-delay and no-exchange-of-information. A complete explicit solution is provided for the first case, and the second is solved in principle.

An Introduction to the N. mPc Design Environment

Abstract: N. mPc, a design tool for multi-processor systems, consists of six components which work together to produce functional register transfer level simulations of multiple processor, heterogeneous target systems. A meta assembler allows the user to specify the format, nmemonics, and associated bit patterns of target instruction sets. Instruction nmemonics are mapped into bit strings and output in a machine independent control/memory allocation graph. A generalized linking loader resolves the machine dependent aspects of assembler output graphs, links, and allocates the resulting image to physical memory according to user specified strategies. A hardware description language , ISP', compiler is used to translate processor and interconnection element descriptions into executable code. This code, the linking loader outputs, and a description of the target system topology are linked by an Ecologist and Simulated Memory Processor into a simulation model which runs under the control of a Runtime Package. The Runtime Package consists of a Command Interpreter, Kernel, and Simulated Memory Manager. The Kernel and Command Interpreter permit interactive control and monitoring of simulations. The Simulated Memory Manager supervises the simulated memory contents, available physical memory, and mass storage to optimize the performance of the simulation. N. mPc is implemented on a PDP-11 system under the UNIX operating system and is currently undergoing system test and evaluation.

The N. mPc System Description Facility

Abstract: N. mPc [1], an interactive environment for the design and evaluation o f microprocessor-based systems, has been developed and implemented at Case Western Reserve University. N.mPc contains five separate tools which work together to produce a functional register transfer level simulation of multiple processor, heterogeneous target systems. A system block diagram is shown in Figure 1.A meta assembler, metaMicro [2], allows the user to specify the Format, mnemonics, and associated bit patterns of the target instruction set. It maps mnemonics into bit strings, and outputs the instructions in a control/memory allocation graph which is machine independent.

PASM: A Partitionable Multimicrocomputer SIMD/MIMD System for Image Processing and Pattern Recognition.

Abstract: : PASM, a Large-scale multimicroprocessor system being designed at Purdue University for image processing and pattern recognition, is described. This system can be dynamically reconfigured to operate as one or more independent SIMD and/or MIMD machines. PASM consists of a Parallel Computation Unit, which contains N processors, N memories, and an interconnection network; Q Micro Controllers, each of which controls N/Q processors; N/Q parallel secondary storage devices; a distributed Memory Management System; and a System Control Unit, to coordinate the other system components. Possible values for N and Q are 1024 and 16, respectively. The control schemes, interprocessor communications, and memory management in PASM are explored. Examples of how PASM can be used to perform image processing tasks are given. (Author)

The N. mPc Runtime Environment

Abstract: Presents the N. mPc runtime environment consisting of the Ecologist, Simulated Memory Processor, Kernel, Command Interpreter, and Simulated Memory Manager. The Ecologist and Simulated Memory Processor assemble the hardware and software modules to form network simulations. The Kernel, Command Interpreter, and Simulated Memory Manager provide the runtime environment The Kernel performs all process scheduling, data structure manipulation, and manages simulation breakpoint and monitor functions. Simulated memories are handled by the Simulated Memory Manager. The interface between the simulation and the user is handled by the Command Interpreter which accepts commands from the user to examine or modify simulation states, to control simulation execution, or to set up data collection from executing simulations.

Effects of buffered memory requests in multiprocessor systems

Abstract: A simulation model is developed and used to study the effect of buffering of memory requests on the performance of multiprocessor systems.A multiprocessor system is generalized as a parallel-pipelined processor of order (s,p), which consists of p parallel processors each of which is a pipelined processor with s degrees of multiprogramming, there can be up to s*p memory requests in each instruction cycle. The memory, which consists of N(=2n) identical memory modules, is organized such that there are l(=2i) lines and m(=2n-i) identical memory modules, where each module is characterized by the address cycle (address hold time) and memory cycle of a and c time units respectively.Too large an l is undesirable in a multiprocessor system because of the cost of the processor-memory interconnection network. Hence, we will show how effective buffering can be used to reduce the system cost while effectively maintaining a high level of performance.

Interleaved Memory Systems with Markovian Requests

Abstract: The disclosure concerns a former for use in a paper making machine, or the like, for producing a web of fibrous suspension on a wire. The former includes a sliding surface, past which a tensioned wire is moved. A duct for fibrous suspension opens on the sliding surface. The sliding surface on the two sides of the duct is shaped so that downstream of the duct in the direction of movement of the wire, a wedge shaped slot is defined between the wire and the sliding surface in which the suspension is received and from which it is dewatered.

Method and apparatus for modifying addresses for the memory control of a one-chip microcomputer having an externally expandable memory

Abstract: A method and an arrangement are disclosed for modifying the addresses of a memory control of a one-chip microcomputer which has an external memory. The address range of the external memory with address values above the address values of the address range for an internal memory is transformed into a value range of 0-2 m , whereby m equals the plurality of connections at the microcomputer by way of which the addresses are output to the external memory.

Dynamic buffer memory control system

Abstract: PURPOSE:To make it possible to perform a corresponding control operation even in case of the mixture of use request, while performing the processing in the alternate buffer system when both buffer memories can be reserved in a memory management routine, and executing transfer by using one buffer memory when only one buffer memory can be reserved. CONSTITUTION:This system is provided with an input/output device such as card reader 16 and a data processing unit consisting of main memory 1 including CPU, and in case of the data read from reader 16 or the data write to reader 16, data is stored in buffer memory 12 temporarily. Here, memory management routine 6 is provided; and in case that the reservation of buffer memories 12-1 and 12-2 is requested to routine 6 by the input/output management system, the processing is performed in the alternate buffer system when both memories 12-1 and 12-2 can be reserved, and transfer is executed with memory 12-1 when only one memory can be reserved. As a result, the corresponding processing operation can be performed even in case of the mixture of use request for buffer memories.

Implementing a bubble memory hierarchy system

Abstract: This paper reports on implementation of a magnetic bubble memory in a two-level hierarchial system. The hierarchy used a major-minor loop device and RAM under microprocessor control. Dynamic memory addressing, dual bus primary memory, and hardware data modification detection are incorporated in the system to minimize access time. It is the objective of the system to incorporate the advantages of bipolar memory with that of bubble domain memory to provide a smart, optimal memory system which is easy to interface and independent of user's system.

The Intelligent Memory System Architecture - Research Directions.

Abstract: : Information storage, retrieval, communication, and processing have become increasingly important for modern command and control systems. Conventional computers are primarily designed for computational purposes and are not well-suited for information management. This report introduces the concepts and research directions of the Intelligent Memory System (IMS), which is particularly designed for large-scale information management to support future command and control systems.

Performance of a virtual memory: some experimental results

Abstract: This paper reports the results of simulation experiment of a model of a virtual memory computer. The model consists of three major subsystems: Program Behavior, Memory Allocation and Secondary Storage. By adapting existing models of these subsystems an overall model for the computer operation is developed and its performance is tested for various design alternatives. The results are reported for different paging devices, levels of multiprogramming, job mixes, memory allocation scheme, page service scheduling and page replacement rate.

Zugriffsfunktionen zur Unterstützung der Speicherverwaltung beim virtuellen Maschinenbetrieb

Abstract: When designing virtual machine systems memory management becomes a problem because the virtual machines must be kept from handling physical addresses. A method is proposed that neither needs much hardware nor does it produce software overhead. This method consists in a set of access functions that are implemented as privileged machine instructions. These instructions are described and their usage is demonstrated using a characteristic example. The implications of the access functions on real machine operation and reconfiguration are outlined and the possible limitations of this approach are discussed.