Showing papers on "Multistage interconnection networks published in 1983"

The Performance of Multistage Interconnection Networks for Multiprocessors

Abstract: This paper studies the performance of unbuffered and buffered, packet-switching, multistage interconnection networks. We begin by reviewing the definition of banyan networks and introducing some generalizations of them. We then present an asymptotic analysis of the performance of unbuffered banyan networks, thereby solving a problem left open by Patel. We analyze the performance of the unbuffered generalized banyan networks, and compare networks with approximately equivalent hardware complexity. Finally, we analyze the performance of buffered banyan networks and again compare networks with approximately equivalent hardware complexity.

Graph Theoretical Analysis and Design of Multistage Interconnection Networks

Abstract: This paper introduces two graph theoretic models that provide a uniform procedure for analyzing 2n-input/2n-output Multistage Interconnection Networks (MIN's), implemented with 2-input/2-output Switching Elements (SE's) and satisfying a characteristics called the "buddy property." These models show that all such n-stage MIN's are topologically equivalent and hence prove that one MIN can be implemented from integrated circuits designed for another MIN. The proposed techniques also allow identical modeling and comparison of permutation capabilities of n-stage MIN's and other link-controlled networks like augmented data manipulator and SW Banyan Network and hence, allows comparison of their permutation. In the case of any conflict in the MIN, an upper bound for the required number of passes has been obtained.

Design and Performance of Generalized Interconnection Networks

Abstract: This paper introduces a general class of self-routing interconnection networks for tightly coupled multiprocessor systems. The proposed network, named a "generalized shuffle network (GSN)," is based on a new interconnection pattern called a generalized shuffle and is capable of connecting any number of processors M to any number of memory modules N. The technique results in a variety of interconnection networks depending on how M nd N are factored. The network covers a broad spectrum of interconnections, starting from shared bus to crossbar switches and also includes various multistage interconnection networks (MIN's).

A Class of Redundant Path Multistage Interconnection Networks

Abstract: A general class of fault-tolerant multistage interconnection networks is presented, wherein fault-tolerance is achieved by providing multiple disjoint paths between every input and output. These networks are derived from the Omega networks and as such retain all the connection properties of the parent networks in the absence of faults. An R-path network in this class can tolerate (R-1) arbitrary faults in the intermediate stages of the network at a cost that is far less than providing R copies of the original network. Different techniques for constructing such networks are presented and relevant properties and control algorithms are investigated.

Fault tolerant capabilities of redundant multistage interconnection networks (multiprocessors)

Abstract: Various methods to introduce alternate paths in multistage interconnection networks to make them more fault tolerant are discussed. Redundant networks such as IADM, IADM with half links, gamma network, extra stage cube network and f-network are described with reference to the number of alternative paths, nature of paths, routing algorithm and their capabilities to survive under single and multiple fault conditions. Comparative merits and demerits in terms of hardware, complexity of routing algorithms and improvements in fault tolerance are discussed. 18 references.

Design of multistage interconnection networks

Abstract: Interconnection networks have extensive applications in switching and reconfigurable multiprocessor systems. A number of multistage networks which can achieve a limited number of permutations have been discussed in the literature [1]. On the other hand, rearrangeable networks [6] have the property that any idle input/output pair can be connected. In most parallel-processing applications, a specified set of input/output connection patterns are required. Often these patterns cannot be achieved by networks like shuffle exchange, cube, Omega and baseline. The chief objective of the paper is to present a methodology for multistage interconnection network design. This design generally requires less switching elements than the rearrangeable network. The paper relies on the formulation of a transmittance matrix for the network. The properties of this matrix are studied with particular focus on rearrangeable networks. A control algorithm which determines the switch states required to achieve a particular permutation is established. The switching algebraic approach is particularly well suited to address the network design problem, because the switch states are explicitly exhibited in the transmittance matrix.

Properties and comparison of multistage interconnection networks for simd machines

Abstract: This thesis investigates some networks that have been proposed for use in SIMD machines, including the omega, augmented data manipulator (ADM), inverse augmented data manipulator (IADM), gamma, and Benes networks. The major results include a count of the number of permutations performable by the ADM and IADM networks, characterizations of the permutations passable by the IADM and gamma networks using particular routing schemes, an investigation into modifying the IADM to permit it to use destination tags, and analysis of simple multiple-pass routing schemes in the omega and IADM networks, showing that the omega network can easily perform the bit-reversal and perfect-shuffle permutations in two passes. We also compare the omega, IADM, and Benes networks, using the criteria of hardware cost, delay time, capability, routing, and fault tolerance. Our main conclusion is that the choice of a network for an SIMD machine depends on when the permutations the network will be required to perform become known. If the permutations are known at compile time, a powerful network with a slow routing algorithm is preferable. The Benes network is in this category. If the permutations are not known until run time, routing in the network must be done quickly. The omega network can be easily controlled using destination tags, and our results show that, for the permutations it cannot perform in one pass, a simple multiple-pass algorithm can be used. Our results on the IADM show that it lies between the two extremes of powerful but difficult to control and easy to control but limited. Therefore, in most applications, the IADM would not be an appropriate network.

Switching strategies in a class of packet switching networks

Abstract: This paper investigates some methods for improving the performance of Single Stage Shuffle Exchange Networks (SENs) and Multistage Interconnection Networks (MINs). The three new switching strategies proposed use extra buffers to enhance performance. Approximate analysis and simulation results indicate significant improvement in performance for both SENs and MINs. An intuitive method for determining the applicability of the approximate analysis is discussed and some performance measures, which should be useful in evaluating the performance of networks are defined.

Fault diagnosis in non-rectangular interconnection networks

Abstract: A method for fault diagnosis in a class of multistage interconnection networks which can be used in a real-time multicomputer system is presented The method allows single and multiple fault diagnosis of regular sw-Banyan networks with arbitrary spread s, arbitrary fanout f, and arbitrary number of levels l, and covers stuck-at-0, stuck-at-1 and bridge type faults in the data and the control parts of the network The method is based on a graph-theoretic approach and can be applied serially for simple fault detection or in parallel for fault detection and location Analytical bounds on the number of tests which are needed for the network diagnosis are given and some implementation issues on the Texas reconfigurable array computer are presented 19 references