Showing papers on "Multistage interconnection networks published in 2023"

4-Disjoint Path Multistage Interconnection Network

Abstract: In many parallel processing systems, multistage interconnection networks (MINs) offer an efficient method of communication between several processors and memory units. There are several fault-tolerant MIN designs in literature. The need to build and construct cost-effective, highly reliable, and fault-tolerant MINs is increasing, nevertheless, as a result of recent developments in parallel computing, which necessitate high processing capacity. In this paper, we proposed a new MIN, called a 4-disjoint path multistage interconnection network (4 DP-MIN). The proposed 4 DP-MIN is using switch chaining to provide a large number of alternate paths, which improves fault tolerance. Using the renowned sum-of-disjoint products (SDP) method and all identified paths, different reliability (2-terminal, broadcast, and network) of the proposed MIN have been evaluated. The proposed 4 DP-MINs' overall performance has also been compared to the other four disjoint paths MINs (4-DGINs) designs in terms of available alternate paths, different reliability metrics, hardware complexity, and the cost per unit.

On Design, Cost and Reliability Analysis of a Fault-Tolerant Multistage Interconnection Network Layout with Six Disjoint Paths

Abstract: Abstract Multistage interconnection networks (MINs) provide an efficient solution for communication between one or more processors and memory modules. These networks are suitable for computationally extensive applications. Although there exist a wide variety of fault-tolerant MIN designs, however there is always a scope of improvement in the design of MINs, which comes with challenges and trade-offs. More specifically there is always a need for fault-tolerant, reliable, and cost-effective designs of MINs, which can tolerate multiple switches and link failures. This always motivates a researcher to focus on various design options and architectural models to enhance performance of the MINs.Designing fault-tolerant MINs requires more disjoint paths from each source–destination (S-D) node pair capability to use all available paths effectively. This paper proposes a new MIN layout viz; 6DP-MIN, which provides six disjoint paths and 14/12 redundant paths for different S-D node pairs. This proposed 6DP-MIN is a modification of gamma interconnection network ( GIN). Performance of the proposed design layout (6-Disjoint Path MIN) has been evaluated in terms of fault-tolerance capability, all available paths, reliability (two-terminal, broadcast, and network), and cost per unit. The results have been compared with other variants of GINs such as SEGIN, SEGLNIN, 3-Disjoint gamma interconnection network, 3- disjoint path multistage interconnection networks, and 4-DGINs. The results suggests that the proposed 6DP-MIN is highly fault-tolerant and reliable with regards to other MINs used for comparison.

Fault Tolerant Gamma-Minus Network

Abstract: In large-scale supercomputers thousands of processors are connected together to their respective memory modules which are controlled by several control units connected in parallel. Large data streams have to be communicated between these processors and memories through interconnection networks. Multistage interconnection network (MIN) is an efficient way to provide these communications at a very reasonable cost. For such large systems MIN employed should be highly reliable and fast to meet the desired specifications of these high speed switch fabrics. In this paper two new architectures of MIN are proposed which are named as fault-tolerant Gamma-Minus (FTGM-1 & FTGM-2) networks. These proposed architectures are multipath MIN with totally disjoint paths and are highly reliable and fault tolerant. The routing algorithm proposed for these structures is simple distance tag routing with non-backtracking which overcomes rerouting overheads and hence improve communication delays. The proposed MIN ensures multiple fault tolerance at each stage including input and output stage with minimal horizontal distance between source node to destination node. For validating the results, a comparison has been presented between existing MINs with these proposed designs. The proposed MINs outperform the existing MIN in terms of reliability, fault tolerance and up to some extent cost as well.

Omega multistage interconnection network manages double-pattern traffic with a regulator and high-speed forwarding method

Abstract: This study proposes a flexible and effective solution for developing high-performance multistage interconnection networks to maximize the performance of parallel computer systems, cloud computing infrastructure, grids, etc. An omega-type multistage interconnection network, consisting of regulated switchboxes, is used as a testbed to handle flexible two-class load patterns. The wormhole routing method and a special forwarding technique controlled by a global regulator are adopted to alleviate internal ‘tree saturation’ caused by periodic hotspot traffic combined with uniform traffic. Simulation experiments prove that this concept reduces packet latency, and an additional layer inserted in the final stage further improves the network’s architecture. GRAPHICAL ABSTRACT