Showing papers on "Phase detector published in 1985"

Fast phase-lock frequency synthesizer with variable sampling efficiency

Abstract: A phase-locked frequency synthesizer (10) having a voltage controlled oscillator (40), a divider circuit (60), and a sample-and-hold phase detector (30, 80, 90, 100, 110) which includes sample-and-hold circuitry (FIG. 6) having variable efficiency. Specifically, the sample-and-hold circuitry provides a sampling pulse of variable width which is controlled to be wider during acquisition and narrower during steady-state operation.

Plasma emission source

Abstract: An impedance matching network for continuously and automatically maximizing RF power transfer to a plasma emission torch includes a dual phase detector network. Signals from the detector network control, via a control unit, a variable impedance network.

Metallic article discriminator

Abstract: A multicoin tester has a coin inlet path 1 along which coins under test run edgewise past coils 2, 3 on opposite sides of the path, and through the windings of a coil 4. Electronic circuitry responsive to the inductive coupling of the coin with the coils operates a gate 5 to either reject the coin onto path 1b or to accept the coin into path 1a. As shown in FIG. 2 each of the coils 2, 3 and 4 is arranged in a parallel L-C resonant circuit 10, 11, 12 connected in the feedback path of an amplifier A1, the resonant circuit being energised sequentially by multiplexer M1. Each of the circuits 10, 11 and 12 has its own natural resonant frequency. The resonant circuits 10, 11, 12 are driven by a voltage controlled oscillator VCO. A phase locked loop including a phase comparator PS1 drives the oscillator VCO at a frequency corresponding to the natural resonant frequency of whichever of the circuits 10, 11 and 12 is connected thereto. As a coin passes say the coil 2, the resonant frequency of circuit 10 is modified by the coin and the phase locked loop changes the frequency of the VCO to maintain resonance. The resulting output at 15 varies both in amplitude and frequency. The amplitude deviation is digitized by an analogue to digital coverter ADC and compared by a microprocessor MPU with stored values in an EEPROM to determine coin acceptability and denomination; so as to operate gate 5 and provide other optional outputs.

Phase responsive composite video signal control system

Abstract: A phase responsive video parameter control system operative for correcting hue, saturation, and luminance of a phase encoded component of a composite video signal. A digital phase detector detects the instantaneous hue of the video image, and provides a signal which selects which one of a plurality of color intervals or bands the detected instantaneous hue falls in. Prestored digital correction values associated with the selected color interval are retrieved from memory and converted into analog correction signals which modify the phase, amplitude, and DC level of the composite video signal. New digital correction values, which reflect operator control panel adjustments, may be loaded into memory during the vertical retrace interval, thereby allowing frame-by-frame color correction.

Battery saving system for a frequency synthesizer

Abstract: A frequency synthesized transceiver capable of tuning to a plurality of communication channels is disclosed. The transceiver includes a receiver and a transmitter section which are coupled to the synthesizer which generates the appropriate injection signals to achieve tuning. A battery saving circuit generates a battery saving signal having a predetermined duty cycle and period and is responsive to the phase detector in the synthesizer to disrupt power to the synthesizer while maintaining precise tuning. The battery saver circuit is also responsive to the transceiver. In a normal receive operation, a battery saving circuit synchronizes its battery saving signal with the hold condition of the phase detector to disrupt power to selected modules in the synthesizer without altering the injection frequency of the receiver. In a standby mode, power is disrupted to all modules in the receiver, the selected modules in the phase locked loop and the voltage controlled oscillator. During a transmit mode all battery saving is terminated.

Digital phase correlator

Abstract: A digital phase correlator compares the relative phase of two or more high-frequency clocks and corrects for any detected phase difference. The phase detector includes a pair of flip-flops whose output is an indication of which of the two clock pulses is leading the other. The output of the flip-flop controls, through a circuit including a rotating shift register and a multitap delay line, the delay introduced to one of the clocks in a manner such that the phase difference between the clocks is reduced to a minimum.

Clock rate spread spectrum

Abstract: A transmitter and receiver for direct sequence spread-spectrum (SS) communications is described. The audio or other analog information to be communicated controls the clock rate of a pseudorandom sequence (PRS) to produce clock rate encoded direct sequence spread spectrum signals. The signals are decoded by a feedback loop including a voltage controlled oscillator which clocks a local PRS generator. A phase detector responds to the clock rate encoded received PRS signal and to the local PRS signal to produce a control signal. The control signal is filtered and applied to the VCO to control the local PRS clock rate. The decoder loop forces the VCO rate to track the clock rate of the encoded signal, and the decoder loop VCO control signal reproduces the analog information. A demodulator for a clock rate encoded SS signal upconverted by a carrier includes a pair of mixers, a first of which receives the signal to be demodulated and the local PRS sequence from the decoder. When the local and received sequence are phase coincident, the first mixer produces the carrier. The second mixer receives the signal to be demodulated and the carrier from the first mixer and generates therefrom demodulated baseband clock rate encoded SS signals for application to the decoder.

Flame protection circuit

Abstract: A flame control circuit becomes a flame protection circuit when the whole circuit is also controlled with respect to correct operation. A final output signal 32 «presence of flame», is supplied only if a flame 6 is present and the circuit operates correctly. In any other case, in which parts of the circuit operate incorrectly, independently of the presence or absence of the flame, the output signal «absence of flame» is supplied. The circuit utilizes the rectifying effect of a flame on an alternating voltage applied to a measuring probe 2 in the flame, and the measuring direct voltage thus obtained, taken with an alternating voltage as reference and applied to correctly polarized phase detection circuits 28, 42 produces the said final output signal.

Circuit arrangement for synchronization of a signal

Abstract: In a circuit arrangement for synchronization of the phase of a frequency-divided signal with an edge of finite slope of an essentially periodic synchronizing signal with an oscillator supplying a clock signal, a frequency divider which generates the frequency-divided signal and a phase detector which comprises a first comparator for coarse phase detection, a second comparator for fine phase detection and a selector circuit which derives a resulting phase signal applied to the oscillator to control the frequency of the clock signal and originating from the first comparator in the case of large phase variations and from the second comparator in the case of small phase variations, precise adjustment to the edge is nevertheless achieved in the case of an amplitude-discrete synchronizing signal with limited time resolution because of the fact that the synchronizing signal is applied to the phase detector as a sequence of amplitude-discrete values which is formed by sampling the synchronizing signal with the clock signal, a sufficient number of amplitude stages being provided for the edge in the synchronizing signal.

Optical information reproducing device

Abstract: PURPOSE:To reduce the fluctuation of an offset of a tracking error signal by obtaining a tracking error signal from the phase difference of output signals from two photodetection cells at the track direction and the other side respectively. CONSTITUTION:The phase difference of photodetector cells A, B is detected by a 1st phase comparator means 11 and the phase difference of photodetector cells C, D is detected by a 2nd phase comparator means 12 respectively and a tracking error detection means 13 detects the tracking error from the sum of the phase differences. In detecting the tracking error, the phase difference of the output signals among the photodetector cells before and after the moving direction of the information track, that is, the photodetector cells A, B and C, D is not affected. Thus, the objective lens is displaced by the tracking control, resulting that the fluctuation of the offset of the tracking error signal is minimized even if the remote visual image 2 is displaced on the photodetector 1.

Phase locked loop circuit

Abstract: PURPOSE:To obtain a phase locked loop PLL having an excellent loop stability by changing the converting gain of a phase comparator in response to the frequency dividing ratio. CONSTITUTION:Plural constant current sources of a phase comparator 2 are controlled by a frequency divider control input 6 via a current source control circuit 7 so as to nearly satisfy Equation, where N1, N2 denote the 1st and 2nd frequency dividing ratios of the frequency dividing ratio N, Kd is the converting gain of a constant current source 1, (a) is a comparison constant, and I2 is a current value of a constant current source 2 (not shown). Thus, the loop gain is made nearly constant by controlling the constant current source of the phase comparator 2 via the circuit 7 as to various N and the stability of the loop is improved. The phase locked loop PLL stable to secular change and temperature change is obtained for digital processing until the constant current source is changed over from the frequency divider control input 6.

Digital sample and hold phase detector

Abstract: The digital sample and hold phase detector to compare the phase relationship between input pulses and a high frequency reference clock comprises a digital counter arrangement coupled to count the high frequency reference clock to produce a digital ramp signal and a digital sampling arrangement coupled to at least the input pulses and an output of the counter arrangement to enable the input pulses to sample the digital ramp signal and produce a digital phase difference signal.

A data frequency modulator with deviation control

Abstract: An automatic deviation control circuit for an angle modulated data transmitter wherein the deviation level of modulated data output from VCO (300) is controlled by a modulation cancelling deviation error detection feedback loop comprising mixer (600), phase detector (408A), low pass filter (410), and VCO (406). After the modulation is cancelled by said feedback loop from a sample of modulated carrier by a predetermined value of deviation developed by divider (302), residual modulation is detected by phase detector (408A), sampled by S/H (808 and 810) following a predetermined number of like-level data bits, and applied to the modulation path gain of amplifier (802) to increase or decrease the deviation such that the residual modulation is minimized.

Telephasing method and system for remotely identifying unknown phases of transmission or distribution lines within an electrical network

Abstract: The telephasing method and system identify an unknown phase within a polyphase network by comparison of the unknown phase with a known reference phase of the polyphase network. The system is especially designed for carrying out the identification of the unknown phase when the reference phase is located at a point of the polyphase network far from the point where the unknown phase is located. The system comprises a first device connected to the reference phase and a second device connected to the unknown phase. The first and second devices each comprise a modem for establishing a telephone connection between the two devices. The first device includes circuitry to produce a digital signal representative of the alternating voltage of the reference phase. This representative signal is transmitted through the two modems and the telephone connection from the first to the second device. The second device comprises circuitry to produce a digital signal representative of the alternating voltage of the unknown phase. The second device is provided with circuits for compensating the transmission delay of the digital signal representative of the alternating voltage of the reference phase transmitted through the telephone connection from the first to the second device. The second device also includes a phase detection circuit for identifying the unknown phase by detecting the phase angle between the alternating voltage of the reference phase and the alternating voltage of the unknown phase.

Voltage Pump Phase-Locked Loops

Abstract: This paper is concerned with the phase-locked loop with Voltage Pump Phase Frequency Detector (VPPFD) and resolves the differences in explanation about its somehow peculiar behavior appearing in the literature.

Tracking control system

Abstract: A tracking control system comprises a capstan motor (19) for moving a magnetic tape (21) which is at least recorded with an FM signal and a control signal having a constant period, a driving circuit (18) for generating a signal which drives the capstan motor, a control head (20) for reproducing the control signal from the tape in a reproducing mode, heads (22) for reproducing the FM signal from the tape in the reproducing mode, a tracking adjuster (27) for generating a comparison signal, a phase comparator (17) for comparing phases of the reproduced control signal with the comparison signal and for generating a phase error signal which is supplied to the driving circuit to control the driving circuit, a sampling circuit (24) for sampling a signal which is based on the reproduced FM signal with a present sampling interval, a discriminating circuit (25) for discriminating levels of sampled data obtained from the sampling circuit, and a circuit (26) for generating a control signal based on a discriminated result in the discriminating circuit and for supplying the control signal to the tracking adjuster to automatically and variably control a duty cycle of the comparison signal so that an envelope level of the reproduced FM signal becomes a maximum.

The N-Phase Digital Tanlock Loop for Tracking Suppressed-Carrier N-ary PSK Signals

Abstract: In this paper, the performance of an N -phase digital tanlock loop (DTL) in the presence of phase error disturbance is studied. The N phase DTL is a digital loop for tracking suppressed-carrier N -ary phaseshift keyed (PSK) signals. It has linear phase characteristics in the modulo- 2\pi/N sense as a result of using the \tan^{-1}[.] function in the phase error detector. We first obtain the probability density function of phase error of the phase detector output and verify it by computer simulation. Then, we consider the optimum bandwidths of the bandpass filters in the loop that yield the minimum variance of the phase error. Also, the finite word length effect on the performance of the N -phase DTL is investigated by computer simulation. In addition, the performance of the N -phase DTL is compared to that of the digital N -phase I-Q loop which has sinusoidal phase characteristics. It has been found that the first-order Nphase DTL has wider lock range than the first-order N -phase I-Q loop in the absence of noise.

Automatic phase control circuit used for time base corrector

Abstract: There is disclosed an automatic phase control apparatus for controlling a phase of a phase information signal used for producing an initial address, the initial address being used for writing into or for reading out from a memory circuit of a time base corrector for reducing a time base error included in a reproduced video signal, including a phase shift circuit for shifting the phase of a horizontal synchronizing pulse, a phase comparator for comparing a phase between the phase shifted horizontal synchronizing pulse and a constant wave signal being in phase with a chroma burst signal and a feedback circuit between the phase comparator and the phase shift circuit for applying a feedback signal in relation to an output signal of the phase comparator to the phase shift circuit so that the phase of the phase information pulse signal is synchronized with the constant wave signal. In this case, the automatic phase control apparatus is characterized by the feedback circuit which includes a capacitor for holding the amplitude of the output signal of the phase comparator, a display circuit connected to the capacitor for indicating the value of the output signal of the phase comparator and a stabilizer circuit connected between the capacitor and a switch circuit for stabilizing the feedback signal so that the value of the feedback signal is approximately zero voltage when the switch circuit is operated.

Laser distance measuring instrument

Abstract: PURPOSE: To accurately and precisely measure the distance to an object by imposing intensity modulation upon laser light with plural frequencies and detecting the phase lag of reflected light obtained by irradiating the object of measurement with modulated light for each frequency. CONSTITUTION: A driving circuit 13 superposes signals of different frequency from oscillators 11 and 12 upon each other to drive an optical modulator 2. The laser light from a laser 1 is modulated with two frequencies to illuminate the object of measurement through a reflecting mirror 5, and reflected light from the object is detected by a photodetector 8. The phase difference between a low frequency component from a band-pass filter and a reference signal from a low frequency oscillator 11 is detected by a phase difference between a high frequency component from a band-pass filter 15 and a signal from the high frequency oscillator 12 is detected by a phase detector 17 to obtain precise distance information, thereby finding the distance to the object accurately over a wide distance range from the two pieces of distance information. COPYRIGHT: (C)1987,JPO&Japio

Double reference pulsed phase locked loop

Abstract: A double reference pulse phase locked loop for measuring the phase shift between tone burst signals initially derived from the same periodic signal source (voltage controlled oscillator 16) and delayed by different amounts because of two different paths A first path is from transducer 12 to surface 14 of sample 11 and back, and a second path is from transducer 12 to surface 15 and back A first pulse phase locked loop including phase detector 26 and phase shifter 22 forces the tone burst signals delayed by the second path in phase quadrature with the periodic signal source A second pulse phase locked loop including phase detector 21 forces the tone burst signals delayed by the first path into phase quadrature with the phase shifted periodic signal source

Uninterruptible polyphase AC power supply

Abstract: An uninterruptible polyphase AC power supply equalizes an electric power taken out from a polyphase AC power source, even if unbalanced load is connected to output. The uninterruptible AC power supply comprizes a polyphase balanced phase shifter generating one control signal in synchronous with one phase of the AC power source and other control signals each having a prescribed phase difference with respect to said former control signal, a phase comparator comparing phases of said respective control signals with those of output voltage of the uninterruptible AC power supply to output correction signals whch minimize the phase difference between them, a plurality of phase shifters for signal phase to which are respectively supplied said control signals as well as said correction signal in the corresponding phases to generate invertor control signals in the corresponding phases, and a means for supplying the invertor control signals being the outputs of said respective phase shifters for single phase to the invertors in the corresponding phases.

Circuit arrangement comprising a voltage-controlled oscillator operable with different sensitivities

Abstract: In a circuit arrangement comprising a power source circuit (12) and a phase detector (22), a phase difference signal (PD) is supplied to a first switch (31) repeatedly turned on and off during battery saving operation and to a second switch (32) initially turned on simultaneously with the first switch. First and second intermediate signals are sent through first and second low-pass filters (41, 42; 43, 44) as first and second modified signals (MO, and M0 2 ), respective-' ly, to a voltage-controlled oscillator (25). A bidirectional nonlinear circuit (36, 37) becomes conductive and also sends the second modified signal to the voltage-controlled oscillator when the first intermediate signal becomes high. The voltage-controlled oscillator produces an oscillation signal with a high sensitivity on supply of both the first and the second modified signals and with a low sensitivity on sole supply of the first modified signal. Such different sensitivities serve to make the circuit arrangement rapidly and stably carry out the battery saving operation.

Clock generator for digital demodulators

Abstract: A clock generator for digital demodulators is disclosed wherein a voltage-controlled oscillator (19) generates clock pulses at controlled frequency and phase in response to error signals from a phase comparator (14) and a frequency comparator (12). The phase error signal represents a phase deviation of the clock from a window pulse which is generated in response to a predetermined transition between binary "1"s and binary "0"s of an input bit stream. The frequency comparator detects the frequency of the clock pulse and compares it with lower and upper limits of a predetermined range of frequency variations and generates a frequency control signal having different voltages depending on the result of the comparison.

Video signal correction system with low chrominance circuit for modifying currections

Abstract: A phase responsive video parameter control system operative for correcting hue, saturation, and luminance of a phase encoded component of a composite video signal. A digital phase detector detects the instantaneous hue of the video image, and provides a signal which selects which one of a plurality of color intervals or bands the detected instantaneous hue falls in. Prestored digital correction values associated with the selected color interval are retrieved from memory and converted into analog correction signals which modify the phase, amplitude, and DC level of the composite video signal. New digital correction values, which reflect operator control panel adjustments, may be loaded into memory during the vertical retrace interval, thereby allowing frame-by-frame color correction.

Phase stabilization for mode locked lasers

Abstract: A method and system for stabilizing the phase relationship of two RF-controlled mode locked lasers involves monitoring the output of both lasers and, with a phase detector/comparator, generating a voltage proportional to the phase difference between the two lasers. The voltage is amplified and filtered and fed into a voltage controlled phase delay connected to the mode locker of one of the lasers. The phase delay operates to delay the RF signal to the one laser according to the desired phase relationship. By disclosed methods and apparatus a single laser can also be stabilized to its own RF drive source to reduce noise effects, two lasers can be individually stabilized to a single RF source, or two lasers can each be stabilized to their own separate RF sources.

Drive circuit for ultrasonic motor

Abstract: PURPOSE:To drive a motor at resonance frequency by simple constitution by setting the frequency of frequency voltage so that a phase difference between a monitor signal from an electrode for monitor and frequency voltage for drive is brought to one on a resonant state at all times. CONSTITUTION:Drive electrodes 1-1, 1-2, an electrode 1-3 for monitor for detecting the resonant state of a stator 1 and a common electrode 1-4 are fitted to a ring-shaped stator 1. Displacement from a predetermined phase difference of a phase difference between an output signal from the electrode 1-3 for monitor and frequency for drive is detected by a phase comparator 12, and an output from the phase comparator 12 is fed to a VCO 5 through a low-pass filter 4, thus determining the frequency of frequency voltage for driving a motor so that a phase difference on a resonant state is brought at all times.

Sync responsive clock generator for digital demodulators

Abstract: A clock generator for digital demodulators is disclosed wherein a voltage-controlled oscillator (19) generates clock pulses at controlled frequency and phase in response to error signals from a phase comparator (14) and a frequency comparator (12). The phase error signal represents a phase deviation of the clock from a window pulse which is generated in response to a predetermined transition between binary "1"s and binary "0"s of an input bit stream. The frequency comparator detects a synchronization code in the input bit stream to derive the frequency error signal by counting the number of clock pulses present in the period of the detected synchronization code.

Phase-locked loop for a directly mixing synchronous AM-receiver

Abstract: A phase-locked loop is constituted by a controllable oscillator coupled through a phase detection arrangement and a low-pass filter to receive an input carrier applied to a signal input of the phase detection arrangement. In order to decrease the phase synchronization between a carrier locally generated in the loop and an input carrier, an unwanted DC offset generated during phase detection is reduced. The phase detection arrangement has first, second and third cascade-coupled mixer stages. An auxiliary mixing signal is applied from a signal generator to the first and third mixer stages. An input of one of the first and second mixer stages is coupled to the signal input of the phase detection arrangement and an input of the other of the two last-mentioned stages is coupled to an output of the controllable oscillator. The low-pass filter has a cut-off frequency lower than the fundamental frequency of the auxiliary mixing signal, and the fundamental frequency is lower than the frequency of the input carrier. The phase-locked loop is used to generate a synchronous RF carrier in a directly mixing AM receiver.

Low order charge-pump filter

Abstract: The present invention discloses a low order charge-pump filter operable with a single variable current source. The integrating capacitor of the charge-pump is connected in an H-bridge switching configuration with four switches that are operable to control the current source to supply current to a first node of the capacitor or to a second node of the capacitor or to bypass a capacitor, depending on the state of operation of the charge-pump. The charge-pump filter disclosed is particularly useful for providing the low order response for a phase detector in a phase-locked loop.

Apparatus for cancelling periodic carrier phase jitters

Abstract: A complex baseband signal is applied to an input termi- nel (1). The carrier phase is protected at successive instance by a phase detector (102) and the most recent set of detected phase values is stored in a shift register (103). Phase predicting means comprise weighting amplifiers (111-113) controlled by correlators (121-123) and a summing circuit (108). The predicted phase signal from the summing circuit (108) is converted by a circuit (109) to a complex trigonometric function with rotates the complex baseband signal by a corresponding phase angle in a phase rotator (104). An error detector (106) detects an error associated with data discriminated from the complex baseband signal. The correlators (121-123) calculate correlations between the detected carrier phases stored in the shift register (103) and the error. A plurality of such circuits may be used for jitter cancellation in a parallel data transmission system using a plurality of complex baseband signals and a pilot signal.