Showing papers on "Phase detector published in 1995"

Digital phase locked loop having coarse and fine stepsize variable delay lines

Abstract: In a digital phase locked loop, a coarse stepsize variable delay line and a fine stepsize variable delay line are connected in series for receiving a reference clock pulse and imparting thereto variable delays in accordance with higher significant bits and lower significant bits. The delayed clock pulse is delivered to the input of a clock tree through which the clock pulse propagates and are supplied to various parts of an integrated circuit chip. A phase detector provides a phase comparison between the reference clock pulse and a delayed clock pulse appearing at one of the outputs of the clock tree. A delay controller counts the reference clock pulse to produce a count value, and increments or decrements the count value in accordance with the output of the phase detector. The up-down count value is supplied as the higher and lower significant bits to the coarse and fine stepsize variable delay lines at such longer intervals than the intervals at which the reference clock pulse occurs, so that the delayed clock pulse is allowed a sufficient time to propagate through the clock tree.

System and method for voltage controlled oscillator automatic band selection

Abstract: A system and method for establishing the frequency of a voltage controlled oscillator ("VCO") within narrowly defined frequency bands. The resonant circuit of the VCO uses selectable elements, such as varactor diodes, to establish the operating frequency band. The control voltage of the VCO is varied within a voltage range to adjust the VCO output frequency. A phase detector compares the VCO output to a reference signal. If the phase detector determines that there is an imbalance between the VCO output and the reference signal, then it produces a signal which indicates whether the VCO frequency should be increased or decreased to match the reference signal frequency. If the control voltage is outside of the voltage range, then the system allows the operating frequency band to be changed by varying the number of selectable elements in response to the phase detector signal.

System and method for phase lock loop gain stabilization

Abstract: The system and method for phase lock loop (PLL) gain stabilization uses a digital compensation technique to correct for the large amount of gain variation present in a voltage controlled oscillator (VCO) utilizing a varactor diode. AVCO is arranged with additional capacitance in parallel with the vatactor diode of the VCO. By using multiple capacitors, more or less capacitance can be switched into parallel with the vatactor diode. Gain variation is accomplished by switching capacitors into the circuit, and for each combination of capacitors used in the resonant inductance-capacitance (LC) circuit of the VCO, the gain of the phase detector in the PLL is adjusted simultaneously. The phase detector has a charge pump that drives a current into a loop filter having a capacitor with a fixed value. The gain adjustment is accomplished by varying the amount of current available from the charge pump to this filter capacitor. The gain compensation circuit that generates this charge pump current takes the same digital code used to control the capacitors in the VCO as an input and performs a digital-to-analog conversion in current mode. The analog current is then transformed into a second-order polynomial via a current squarer and programmable current scalers to provide a gain compensation signal for the phase detector. The programmable current scalers determine the coefficients of the second order polynomial. Therefore, for any given VCO characteristic with regard to the additional capacitors and the varactor diode, the coefficients of the current scalers can be adjusted to accommodate a more precise PLL gain control.

Apparatus and method for measuring the phase and magnitude of microwave signals

Abstract: A measurement system is provided which comprises: source circuit for receiving feedback signals and for providing respective signals at respective discrete frequencies in a prescribed microwave frequency range, wherein the respective provided signals at respective discrete frequencies are substantially phase locked to at least one downconverted signal in response to the feedback signals; downconverting circuit for linearly downconverting the respective provided signals and for providing the at least one respective downconverted signal; and phase detector circuit for receiving the at least one respective downconverted signal and for providing the feedback signals.

Digital variable in-lock range phase comparator

Abstract: A novel method and apparatus providing an all digital phase comparator of two binary signals which employs a type of cross correlation of two binary signals and provides a 2bit binary word uniquely representative of phase alignment The method can be carried out using a pair of flip-flop (FF) circuits, each FF having a docking input and a data input, and where each FF has a delay in series with its data input

A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip

Abstract: Many high energy physics and nuclear science applications require sub-nanosecond time resolution measurements over marry thousands of detector channels. Phase-locked loops have been employed in the past to obtain accurate time references for these measurements. An alternative solution, based on a delay-locked loop (DLL) is described. This solution allows for a very high level of integration yet still offers resolution in the sub-nanosecond regime. Two variations on this solution are outlined. A novel phase detector, based on the Muller C element, is used to implement a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge of an input clock reference. This greatly reduces timing jitter. In the second variation the loop locks to both the leading and trailing clock edges. In this second implementation, software coded layout generators are used to automatically layout a highly integrated, multi-channel, time to digital converter (TDC). Complex clock generation can be achieved by taking symmetric taps off the delay elements. The two circuits, DLL and TDC, were implemented in a CMOS 1.2 /spl mu/m and 0.8 /spl mu/m technology, respectively. Test results show a timing jitter of less than 35 ps for the DLL circuit and better than 135 ps resolution for the TDC circuit.

Phase lock loop having a reduced synchronization transfer period

Abstract: A phase lock loop has a lock detection circuit, a phase comparator, a charge pump circuit, a low-pass filter, a variable delay circuit and a frequency divider. The lock detection circuit generates a lock detection signal when a phase difference between an input reference clock and an output of the variable delay circuit is smaller than a predetermined value in a first stage of the synchronization operation. The input and output of the variable delay circuit are connected in a loop responding to the lock detection signal to form a voltage controlled oscillator (VCO) and shift the phase lock loop into a second stage of the synchronization operation. An initial control signal for controlling the VCO in the second stage is obtained as a value of the variable delay circuit in the first stage before generation of the lock detection signal, thereby obtaining a higher-speed synchronization operation and low jitters in the output clock.

A Novel Technique for Spatial Phase-shifting Interferometry

Abstract: A novel technique for phase detection using three-step spatial phase-shifting interferometry is presented. The presented technique overcomes and studies the two main problems presented in the commonly used three-step phase-stepping technique. These problems deal with the leak of carrier frequency in the detected phase and the optimal carrier frequency to obtain the highest phase noise robustness.

Jitter measurement apparatus detecting amplitude of phase errors between information signal and synchronized clock signal

Abstract: A read-out information signal read out from an optical disk carrier is digitized, thereby detecting an amplitude of an absolute value of a phase error between the read-out information signal and a synchronized clock signal. The synchronized clock signal is obtained by using a phase locked loop constituted by a phase detector having two outputs, that is, a phase lead and a phase lag, and a VCO operating at an average value of a differential signal representing a difference between the two outputs. A phase error amplitude is detected from a sum signal representing a sum of the two outputs of this phase detector. By appropriately displacing a focus actuator in a state where a focus control is performed, an offset compensation amount where the phase error amplitude becomes minimum is obtained.

Means for control limits for delay locked loop

Abstract: A delay lock loop having an improved delay element which results in a two-fold improvement in the operation of the delay lock loop. Firstly, it guarantees that the phase detector portion of the delay lock loop will yield the correct phase differential. Secondly, it eliminates the possibility of a harmonic lock condition from occurring.

High frequency receiving apparatus

Abstract: A high frequency television signal receiving apparatus providing excellent linear detection of output characteristics by improving the phase characteristic of the picture synchronous detector. A variable capacitive element is equivalently connected in parallel to a reference solid-state oscillation element. The reference solid-state oscillation element controls the frequency of a local oscillation device including a PLL circuit for feeding a local oscillation signal to a mixer for converting a high frequency signal into an intermediate frequency signal. A first low pass filter is connected between a phase comparator for detecting a phase difference of the intermediate frequency signal and the output of a detection oscillator for generating a detection oscillation signal with a specific phase difference. A second low pass filter having a larger time constant than the first low pass filter is connected to the variable capacitive element. The capacitance of the variable capacitive element is varied by the output voltage of the phase comparator. The signal frequency of the local oscillation device is shifted, and is controlled to converge the frequency of the intermediate frequency signal within the frequency range of the detection oscillation signal.

Frame synchronizing apparatus for quadrature modulation data communication radio receiver

Abstract: In a frame synchronizing apparatus for a receiver apparatus of a digital data radio communications system in which data are transmitted in frame periods with a fixed data sequence contained each frame, a data correlation circuit obtains successive sequences of values of vector difference between vector values constituting a demodulated digital baseband signal, and successively compares these sequences with a fixed vector difference sequence corresponding to the fixed data sequence, to derive a correlation signal substantially unaffected by any phase rotation in the baseband signal. A frame synchronizing circuit formed as a PLL for generating a frame synchronizing signal, includes a phase comparator which periodically indicates whether a detected phase difference between the correlation signal and frame synchronizing signal is effectively zero, positive or negative, and a counter holding a count value indicating a cumulative phase error between these signals. So long as the detected phase differences are successively effectively zero and the cumulative phase error is sufficiently small, the phase of the frame synchronizing signal is held unchanged, thereby achieving a high degree of phase stability.

Carrier independent timing recovery system for a vestigial sideband modulated signal

Abstract: A television signal receiver for processing an HDTV signal transmitted in a vestigial sideband (VSB) format includes input complex filters shared by a timing recovery network (30) and a carrier recovery network (50). The filter network includes a pair of upper and lower band edge filters (20, 22) mirror imaged around the upper and lower band edges of the VSB signal for producing suppressed subcarrier AM output signals. The timing recovery network includes a phase detector (28, 38, 62) and responds to an AM signal derived from the two filters (via 26) for synchronizing a system clock (CLK). The carrier recovery network (50) also includes a phase detector (54, 60, 62, 64), and responds to outputs from one or both of the filters for producing an output error signal (Δ) representing a phase/frequency offset of the VSB signal. The error signal is used to reduce or eliminate the offset to produce a recovered baseband or near baseband signal. A subsequent equalizer eliminates any residual phase offsets in the recovered signal.

Blind equalizer for a vestigial sideband signal

Abstract: A television signal receiver for processing an HDTV signal transmitted in a vestigial sideband (VSB) format with a one-dimensional data constellation includes a first carrier recovery network (18), an equalizer (20), and a second carrier recovery network (22, 30, 62). A multiple stage quantizer network (50, 66) exhibiting progressively finer resolution is associated with the operation of the equalizer for providing blind equalization without need of a 'training' signal. The second carrier recovery network includes a phase detector (30) wherein a one-symbol delayed (312) input signal and a quantized (310) input signal are multiplied (316), and an unquantized input signal and a quantized (310) one-symbol delayed (314) input signal are multiplied (318). Signals produced by the multiplication are subtractively combined (320) to produce an output signal representing a carrier phase error.

Carrier recovery system for a vestigial sideband signal

Abstract: A television signal receiver for processing an HDTV signal transmitted in a vestigial sideband (VSB) format includes input complex filters shared by a timing recovery network (30) and a carrier recovery network (50). The filter network includes a pair of upper and lower band edge filters (20, 22) mirror imaged around the upper and lower band edges of the VSB signal for producing suppressed subcarrier AM output signals. The timing recovery network includes a phase detector (28, 38, 62) and responds to an AM signal derived from the two filters (via 26) for synchronizing a system clock (CLK). The carrier recovery network (50) also includes a phase detector (54, 60, 62, 64), and responds to outputs from one or both of the filters for producing an output error signal (Δ) representing a phase/frequency offset of the VSB signal. The error signal is used to reduce or eliminate the offset to produce a recovered baseband or near baseband signal. A subsequent equalizer eliminates any residual phase offsets in the recovered signal.

Radar sensor/processor for intelligent vehicle highway systems

Abstract: A radar sensor/processor for intelligent vehicle highway systems. The radar sensor/processor provides the range, speed, identity of, and selective communications with, vehicles equipped with a transponder in a first cooperative interrogator/transponder mode, and provides information on the range and speed of vehicles without a, or with an inoperative, transponder in a second noncooperative mode. The interrogator includes a first direct digital synthesizer, with an associated first input binary tune register, for producing a sine wave output, a multiplier for multiplying the sine wave output to produce an X-band signal, and a bi-phase single sideband modulator which modulates the X-band signal with data to be transmitted. The interrogator receiver receives a returned transponder reply signal, and includes a balanced mixer for downconverting the reply signal. A down-converted carrier signal is extracted, and is an input to a control loop which includes a second direct digital synthesizer, its associated second input binary tune register, a phase detector, and an A/D converter. The control loop rapidly adjusts the count in the second binary tune register to bring the output frequency of the second direct digital synthesizer into exact correspondence with the down-converted carrier signal. A subtraction of the respective counts in the input binary tune registers for the first and second direct digital synthesizers is a measure of the vehicle speed.

Steered frequency phase locked loop

Abstract: A Steered Frequency Phase Lock Loop (SFPLL) comprises a phase loop that functions like a normal phase locked loop (PLL) and locks to the input signal, and a frequency loop that uses a reference frequency to influence the phase loop and effectively confines the output frequency of the phase loop and the SFPLL to be in a range of frequencies close to the reference frequency. The reference frequency is chosen to be very close to the input signal frequency that it is desired the SFPLL lock to. The SFPLL comprises a phase detector (10), a frequency detector (22), first and second gain components (12, 24), first, second and third filter components (14, 18, 26), a summer (16) and a voltage controlled oscillator (VCO) (20). By a judicious choice of the gains in the phase and frequency loops the SFPLL can be designed so that the range of frequencies to which the SFPLL will lock can be confined to an arbitrarily small region around the reference frequency ( omega 'r). Applications of the SFPLL include demodulation in CW modulation systems and timing recovery from NRZ data. Three advantages of the SFPLL are that the output frequency is equal or close to the reference frequency when no input signal is present, and the range of frequencies to which the SFPLL can lock is confined to a region around the reference frequency, and the phase and frequency instabilities of the VCO can be reduced.

Phase detector in a carrier recovery network for a vestigial sideband signal

Abstract: A television signal receiver for processing an HDTV signal transmitted in a vestigial sideband (VSB) format with a one-dimensional data constellation includes a first carrier recovery network (18), an equalizer (20), and a second carrier recovery network (22, 30, 62). A multiple stage quantizer network (50, 66) exhibiting progressively finer resolution is associated with the operation of the equalizer for providing blind equalization without need of a "training" signal. The second carrier recovery network includes a phase detector (30) wherein a one-symbol delayed (312) input signal and a quantized (310) input signal are multiplied (316), and an unquantized input signal and a quantized (310) one-symbol delayed (314) input signal are multiplied (316), and an unquantized input signal and a quantized (310) one-symbol delayed (314) input signal are multiplied (318). Signals produced by the multiplication are subtractively combined (320) to produce an output signal representing carrier phase error.

Modified bang-bang phase detector with ternary output

Abstract: A phase detector is described. The phase detector receives a data signal from an external circuit. The phase detector generates a first signal when a transition edge of the clock signal occurs after a transition edge of the data signal. The phase detector generates a second signal when the transition edge of the clock signal occurs before the transition edge of the data signal and generates a third signal when the data signal remains in a same signal state for at least two transition edges of a same type of the clock signal.

N-phase modulated signal demodulation system with carrier reproduction

Abstract: A phase modulated signal demodulation system which is not affected by noise and distortion of an input signal. The system includes a carrier reproduction PLL circuit for generating a reproduction reference clock having a frequency which is N times of a carrier frequency which is synchronized with an N-phase phase modulated input signal, and a clock generation circuit for dividing the reproduction reference clock by 1/N and for generating N clocks, each of which has a different phase offset by 360°/N. The system further includes a phase detector which detects a phase of the N-phase phase modulated signal by using the N clocks together with the input N-phase phase modulated signal; and an operating circuit which detects a data edge of the input signal and the reproduction reference clock. The system further includes a data clock reproduction PLL circuit for generating a clock synchronized with a data rate using an output from the operating circuit, and a second clock generation circuit which generates a plurality of clocks for majority judgments using an output of the data clock reproduction PLL circuit. The system further includes a data protection circuit for protecting data generated by the phase detector, and a data generating circuit which outputs a corresponding digital data according to phase information outputted from the phase detector.

Timing recovery controller and method for adjusting the timing of synchronizing windows in a PSK demodulator

Abstract: A digital demodulator and method for demodulating digital data representing a phase shift keyed (PSK) signal are provided. The demodulator comprises a phase detector, automatic frequency controller, automatic timing recovery controller, data decoder, and unique word detector. According to the method of the present invention, a PSK signal is received and digitized to substantially remove the signal's amplitude characteristics. The phase detector receives an input of the digital data and based upon transitions in the data from a high state to low state and from a low state to a high state, provides phase estimates. The phase estimates are converted by the data decoder into binary data representing the symbols transmitted to form the PSK signal. A number of overlapping windows of digital data are used to determine phase estimates. The unique word detector receives an input of binary data from the data decoder and using a correlation technique identifies one set of windows which substantially maximizes synchronization of the demodulator with the received PSK signal. After the synchronizing window has been identified the automatic frequency controller monitors any frequency drift of the PSK signal and corrects the phase estimates based on the frequency error. The automatic timing recovery controller uses the corrected phase errors from early and late windows with respect to the synchronizing window to adjust the timing of the synchronizing window by advancing or delaying the demodulator's symbol timing signal to further maximize synchronization with the received PSK signal.

Picosecond-accuracy all-optical bit phase sensing using a nonlinear optical loop mirror

Abstract: We demonstrate picosecond-accuracy bit phase comparison using a nonlinear optical loop mirror. We use this all-optical bit phase comparator to synchronize an external cavity modelocked diode laser operating at 10-GHz to a soliton compression source operating at 10-GHz using an electrooptic phase lock loop. We believe this is the first demonstration of soliton compression source synchronization. The holding range of the phase lock loop is /spl plusmn/20 MHz, and is limited by the modelocking bandwidth of the external cavity laser. Clock acquisition time is dominated by the latency of the nonlinear optical loop mirror. >

Automatic frequency control method and apparatus therefor

Abstract: An automatic frequency control apparatus used in an MPSK communication system detects a frequency offset between a carrier and a local oscillation signal for adjustment of a local oscillation frequency. A phase difference detector generates a first phase difference detection signal having, as a phase value, a difference between the phases of various samples of the sampled signal. A phase altering unit generates a second phase difference detection signal having a phase value different from that of the first phase difference detection signal. A frequency offset signal generator estimates transmission phase information by using the phase value of the second phase difference detection signal and reference phase signals used for MPSK modulation, thereby generating a frequency offset signal which is determined by the transmission phase signal and the second phase difference detection signal. The result is that the number of the reference phases which are used for determination of the transmission phase information by altering the phase of the phase difference signal, is reduced. Accordingly, the hardware cost for implementing the apparatus can be lowered. The invention can be used for automatic frequency control in a modem which is used for all the types of MPSK modulation.

Phase synchronizer and data reproducing apparatus

Abstract: A phase synchronizer is disclosed that provides a stable output signal while improving synchronization speed. The phase synchronizer includes one or two feedback circuits. The feedback circuit(s) includes a phase comparator for generating a pulse signal in accordance with a difference between the phases of an input signal and a feedback signal, a charge pump for converting the pulse signal supplied from the phase comparator to an analog voltage signal, a loop filter for removing high-frequency signal components from the analog voltage signal output from the charge pump and supplying as a filtered analog voltage signal (LF1 or LF2), and a voltage-controlled oscillator coupled to the loop filter for generating an oscillation output signal having a frequency which varies in accordance with the filtered analog signal (LF1 or LF2). The oscillation output signal is also supplied as the feedback signal to the phase comparator.

Novel measuring system for oxygen micro-optodes based on a phase modulation technique

Abstract: New fiber optic oxygen microsensors (microoptrodes) for use in aquatic environments have recently been developed as an alternative to commonly used CLark-type oxygen microelectrodes. The microoptrodes have the advantage of no oxygen consumption and no stirring sensitivity combined with a simple manufacturing process of the sensors. To avoid problems inherent to luminescence intensity measurements like photobleaching, signal dependency on the optical properties of the surrounding medium and system drifts, a novel measuring system was developed. This system uses a phase modulation method to evaluate a signal phase shift that is caused by the oxygen dependent luminescence lifetime. The measuring system is based on simple solid state technology. High reliability and low costs of the system can therefore be combined with the ability of miniaturization and low power consumption. The system consists of three units: 1) the microoptrode with the optical setup [glass fiber coupler, optical filters, lenses, light source (light emitting diode) and light detection (photon multiplier tube)], 2) the analogue signal processing unit, including a special phase detection module, and 3) the digital signal processing unit, a personal computer or a microcontroller for control of the measuring system, display and data storage. First measurements of oxygen depth profiles in sediments and biofilms at high levels of ambient light demonstrated the advantages of phase shift based O2 measurements as compared to intensity based measurements with microoptrodes.© (1995) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Optical synchronization arrangement

Abstract: In a sychronizing arrangement for synchronizing two streams of optical pulses, the problem arises that for pulse frequencies above 10 GHz the operation of the synchronizing arrangement becomes increasingly difficult. To overcome that problem it has been proposed to use a phase locked loop having an optical phase detector, but prior art optical phase detectors have low efficiency and was rather complex. According to the invention an optically controlled optical switch is used as the phase detector.

Linearizing device for a frequency-modulation ramp and its application to a radio altimeter

Abstract: The invention relates to a device for the linearization of a frequency modulation ramp comprising a voltage controlled oscillator associated with a phase locked-loop. The device comprises a digitally controlled oscillator of which only the most heavily weighted bit is used, and a digital phase comparator receiving, on the one hand, said most heavily weighted bit and, on the other hand, a signal supplied by the voltage controlled oscillator. Application to very high linearity and very high accuracy radio altimeters.

Electrical signal jitter and wander measurement system and method

Abstract: An electrical signal jitter and wander measurement system (30) operates in real time and digitally controls bandwidths over which the measurements are performed. A digital phase-lock loop ("PLL") (34) includes a phase detector (44), low pass filters (48, 56), an analog-to-digital converter ("ADC") (54), a digital signal processor ("DSP") (32), a direct digital synthesizer ("DDS") (38), and a tracking oscillator (39). The phase detector receives an input signal that is compared with a signal derived from the DDS. The phase detector signal contains wander and jitter data that are filtered and digitized by the ADC. The DSP receives the data and performs a proportional integral control function to lock the PLL by digitally controlling the DDS frequency. The DDS generates a clock signal at a precise rate determined by the phase accumulation registers. The tracking oscillator locks to multiples of the DDS frequency to increase the resolution of the phase measurement. A master reference clock (40) controls the PLL with a stability and accuracy sufficient to measure low frequency wander. Wander data are available from the DSP as an integral of the DDS operating frequency. The DSP also performs the required loop filter function and high pass filters the wander data to provide subband jitter data. This invention digitally controls the PLL filter high pass bandwidth down to very low frequencies to accurately measure low frequency jitter and wander.

High-speed bit synchronizer with multi-stage control structure

Abstract: A high-speed bit synchronizer comprising a phase comparator for detecting a phase relationship between a center of an eye pattern of input NRZ data and a rising transition of a clock pulse from a voltage controlled oscillator (VCO) whenever the input NRZ data makes a transition, a frequency comparator for detecting a frequency relationship between a multiple of a period of the clock pulse from the VCO and a multiple of a period of an external reference clock pulse whenever the external reference clock pulse makes a rising or falling transition, phase and frequency comparator gain limiters for limiting gains of the phase and frequency comparators, respectively, a frequency synchronous signal detector for generating frequency synchronous and asynchronous signals in response to an output of the frequency comparator, a phase difference output controller for controlling the transfer of an output of the phase comparator gain limiter in response to an output of the frequency synchronous signal detector, a low pass filter (integrator) for outputting a voltage of a low frequency component to the VCO in response to an output of the phase difference output controller and an output of the frequency comparator gain limiter, and a frequency-divider for frequency-dividing the clock pulse from the VCO at a desired ratio.

A 250-622 MHz deskew and jitter-suppressed clock buffer using a frequencyand delay-locked two-loop architecture

Abstract: Recently, several delay-locked loop (DLL) circuits for on-chip clock supply have been reported. In this paper a new 2-loop circuit has been designed for on-chip clock-supply applications which require a quick pull-in, suppressed jitter in a wide operating frequency range. The design technologies included are: 1) A 2-loop architecture in which a frequency-locked loop (FLL) is provided separately from a DLL for quick pull-in over a wide frequency range; 2) A current-mode phase detector (CMPD) used in the DLL, which makes use of a flip-flop metastability for increasing the phase-difference detecting sensitivity.