Showing papers on "Pipeline (computing) published in 1977"

Pipeline Architecture

Abstract: Pipelined computer architecture has received considerable attention since the 1960s when the need for faster and more cost-effective systems became critical. The merit of pipelining is that it can help to match the speeds of various subsystems without duplicating the cost of the entire system involved. As technology evolves, faster and cheaper LSI circuits become available, and the future of pipelining, either in a simple or complex form, becomes more promising.This paper reviews the many theoretical considerations and problems behind pipelining, surveying and comparing various representative pipeline machines that operate in either sequential or vector pipeline mode, the practical solutions adopted, and the tradeoffs involved. The performance of a simple pipe, the physical speed limitation, and the control structures for penalty-incurring events are analyzed separately. The problems faced by the system designers are tackled, including buffering, busing structur, branching, and interrupt handling. Aspects of sequential and vector processing are studied. Fundamental advantages of vector processing are unveiled, and additional requirements (costs) are discussed to establish a criterion for the tradeoff between sequential and vector pipeline processing. Finally, two recent machines (the CRAY-1 and the Amdahl 470 V/6 systems) are presented to demonstrate how complex pipeline techniques can be used and how simple but advantageous pipeline concepts can be exploited.

A Data Flow Multiprocessor

Abstract: This paper presents the architecture of a highly concurrent multiprocessor which runs programs expressed in data flow notation. Sequencing of data flow instruction execution depends only on the availability of operands required by instructions. Because data flow instructions have no side effects, unrelated instructions can be executed concurrently without interference if each has its required operands. The data flow multiprocessor is hierarchically constructed as a network of simple modules. All module interactions are asynchronous. The principal working elements of the machine are a set of activation processors, each of which performs the execution of one invocation of a data flow procedure held in a local memory within the processor. A pipeline of logical units within each processor executes several concurrently active instructions. All data flow operations are performed within single processors except procedure calls, which cause the creation of new activations in other processors, and operations on large data structures, which are performed by structure controller modules using values stored in a central memory. Concurrency within a data flow procedure provides a processor with something to do while a slow operation is being processed. The behavior of the machine has been specified by a formal description language and has been shown to correctly implement the data flow language. The principal advantages of the data flow multiprocessor over conventional designs are reduced complexity of the processor-memory connection, greater use of pipelining, and a simpler representation and implementation of concurrent activity.

An instruction timing model of CPU performance

Abstract: A model of high-performance computers is derived from instruction timing formulas, with compensation for pipeline and cache memory effects. The model is used to predict the performance of the IBM 370/168 and the Amdahl 470 V/6 on specific programs,/and the results are verified by comparison with actual performance. Data collected about program behavior is combined with the performance analysis to highlight some of the problems with high-performance implementations of such architectures.

Template micromemory structure for a pipelined microprogrammable data processing system

Abstract: In a microprogrammed data processing pipeline system comprising a plurality of stages, microinstructions for controlling the stages are stored as templates in an addressable template micromemory store and are provided automatically and sequentially to the stage of the pipeline system. Each template is associated with an individual set of data and includes microinstructions for each stage, whether real or virtual, through which the associated set of data passes. The template micromemory store is segmented into a plurality of individually addressable micromemory units with each unit therein storing microinstructions for an individually associated stage in the data processing pipeline system.

Model, Design, and Evaluation of a Compiler for a Parallel Processing Environment

Abstract: The problem of designing compilers for a multiprocessing environment is approached. We show that by modeling an existing sequential compiler, we gain an understanding of the modifications necessary to transform the sequential structure into a pipeline of processes. The pipelined compiler is then evaluated through measurements and simulation. Properties of the model, a generalized Petri Net, are also discussed.

The microprogramming of pipelined processors

Abstract: A pipelined processor is one whose computational capabilities are divided into several sequential stages, each of which may be working with an independent set of data at the same instant of time. Such processors are capable of handling large streams of data at very high rates. As with conventional CPUs, the microprogrammed control of such processors offers advantages not possible with hardwired controls. This paper discusses some unique tradeoffs that may be made in the design of microprogrammed pipelines. A sample pipeline demonstrates the characteristics of two extremes of microprogrammed control—one where the microinstruction specifies all activity in the pipeline at one instant of time (time-stationary) and one where the microinstruction “follows” the data through several clock periods (data-stationary). Several typical microprograms show the effects of these two variations on hardware costs, microprogrammability, and pipeline efficiency.

Eddy current generating type metal pipeline detector

Abstract: A metal pipeline detector is described in which a generator generates a magnetic field. The magnetic field couples the metal pipeline when the detector is located in the vicinity thereof, and as a result eddy currents are induced in the pipeline. Detector coils are arranged to be coupled by the magnetic field produced by the eddy currents but not by the magnetic field generated by the generator. The detector coils are spaced apart so that the magnitude of the field coupled in each coil is representative of the distance between the pipeline and the coil. Electrical processing circuitry acts to detect the difference between the magnetic field coupled in each coil so as to determine the degree of which the detector is displaced from the optimum path for tracking the pipeline. In addition the processing means acts in response to the outputs of the detector coils to provide an indication of the distance of the pipeline to the detector.

Microprogrammed computer control unit capable of efficiently executing a large repertoire of instructions for a high performance data processing unit

Abstract: A cache oriented pipeline data processing unit includes an execution unit, apparatus for fetching data and instructions, hardware decoder and sequencing circuits and a microprogrammed control unit. The microprogrammed control unit includes first and second control stores. The first control store includes a plurality of storage locations, each location for storing at least an address field and a control sequence field for each of the program instructions required to be executed by the data processing unit. The control sequence field is coded to designate which one of a group of hardware control sequences is to be executed by the hardware sequencing circuits for matching the performance of the execution unit and fetching apparatus. The second control store includes a plurality of groups of storage locations, each group for storing the microinstructions required for executing at least a portion of a program instruction. The microprogrammed control unit in response to each instruction op-code reads out signals corresponding to a control sequence field which are decoded to condition the hardware sequencing circuits for performing those operations required for execution of the instruction. The starting location in the second control store is referenced at the end of the designated hardware sequence and instruction execution proceeds under microprogram control.

Multibus processor for increasing execution speed using a pipeline effect

Abstract: A computing apparatus having at least three buses and a plurality of elementary function modules in circuit connection therewith, provides increased execution speed by implementing a pipeline effect. Each module is connected to at least one of the buses and at least one of the modules is connected to at least three of the buses. The buses each comprise a plurality of individual lines organized into groups: a group of source address lines, a group of destination address lines, and a group of data carrying lines. A control element is connected to each of the buses for directing the operation of the apparatus and the control element places source and destination addresses on the bus source address and destination address lines respectively for effectively connecting or configuring the function modules according to a selected program controlled configuration. The apparatus is useful in carrying out a plurality of machine operations during a single machine instruction cycle.

A multi-microprocessor implementation of a general purpose pipelined CPU

Abstract: This paper discusses and shows by example the potential of a network of microprogrammable microprocessors as a cost-effective alternative to traditional hardwired medium- and large-scale mainframes. While biased towards vector processing, this system is not intended to compete with multi-million dollar supercomputers such as the 360/195, CDC STAR, Illiac IV, CRAY-1, TI ASC, etc., which use special algorithms and the fastest circuitry available.The architecture incorporates pipelining, multiprocessing and distributed processing techniques with bipolar microprocessor technology. The result should be a machine which will equal or outperform most traditional third- and fourth-generation mainframes at a fraction of the CPU cost. This should be the case even for scalar, general purpose computation.

Hardware controlled transfers to microprogram control apparatus and return via microinstruction restart codes

Abstract: A microprogrammed pipeline data processing unit includes a first control store, a second control store and a plurality of hardware sequence control circuits. The first control store includes a plurality of storage locations, each location for storing an address field and a control sequence field for each program instruction required to be executed by the processing unit. The second control store includes a plurality of groups of storage locations, each group storing microinstructions required for executing at least a portion of at least one program instruction. Each sequence includes at least one microinstruction which contains a restart field coded to specify the conditions under which the hardware sequence circuits continue instruction execution. For each program instruction which can not be executed by the plurality of hardware sequence circuits in a pipeline mode, the control sequence field is coded to include a predetermined bit pattern. When decoded, the hardware sequence circuits is conditioned to enter an escape state enabling control to be transferred to a sequence specified by the address field. Instruction execution proceeds under microprogram control while the hardware sequence circuits remain in the same state. Upon the decoding of a microinstruction containing a restart field, the hardware sequence circuits are switched from the escape state to a state which enables the continuing of hardware instruction execution in a pipeline mode.

Apparatus and method for towing a pipeline in a body of water

Abstract: An apparatus and method for towing a pipeline in a body of water to a place where the pipeline is to be laid on the bed of the body of water, the pipeline having a positive buoyancy and being provided with trail-ropes distributed therealong which drag on the bed while the pipeline is being towed and maintain it at a certain distance above the bed, wherein some at least of the trail-ropes are connected to the pipeline at points spaced apart therein in such manner that such trail-ropes are formed with arcuate portions extending between the points of attachment to the pipeline so that when said arcuate portions drag upon the bed they are retained substantially parallel to the longitudinal axis of the pipeline thereby to oppose drift by a transverse current, said trail-ropes also optimally comprising means for penetrating the bed so as to offer increased resistance to drift.

Method and apparatus for adjusting the tension of an underwater pipeline

Abstract: A system for measuring and displaying the side and top profiles of an underwater pipeline as the pipeline is being laid on the sea floor by a pipe laying vessel. The profiles are determined by sequentially measuring the position of points spaced apart along the pipeline with respect to a point on the vessel. The measurements are accomplished by sequentially transmitting an acoustic signal from three, non-colinear transducers. The acoustic signals from each transmission is detected by a plurality of receivers spaced apart along the pipeline. As each receiver detects a transmission it produces an indicating signal on a pair of electrical conductors which are connected to the vessel and all of the receivers on the pipeline. The elapsed time between a transmission from a given transducer and detection of that transmission by each receiver is an indication of the distance between the transducer and each receiver. After all three transducers have interrogated the receivers, the three-dimensional position of each receiver is known, and the pipeline profile as viewed from the top and side can then be platted. Examination of the pipeline profile indicates the stress along the pipe so that the pipeline tension, or barge yaw attitude, can be adjusted to prevent damage to the pipeline.

Apparatus for transporting heavy equipment on a pipeline

Abstract: Apparatus is disclosed for transporting heavy equipment such as welding current generators, a prime mover therefor, and associated devices or supplies, on and along a pipeline, the pipeline serving as a monorail. The apparatus, of elongated construction along the pipeline, is supported at one end and propelled along the line by power driven traction means engaging the top part of the pipeline. The opposite end of the apparatus is supported on a pair of laterally spaced swivel mounted wheels which engage the sides of the pipeline laterally away from and somewhat below the top of the line. The latter wheels give lateral support and stability to maintain the apparatus in a substantially upright position on the pipeline. Sensing means, such as a pendulum, mercury switch means, or equivalent, detect incipient tilting or motion towards instability and are used to steer the swivel mounted wheels, either directly or indirectly. Indirect steering is accomplished through auxiliary side wheels which are directed to raise one side and lower the other of the apparatus to restore it to upright position when needed. Hydraulically operated pipe gripping means are provided to clamp the apparatus to the pipeline when it is not traveling, as during a welding operation.

Fluid sensitive shutdown for well pump

Abstract: A system for disconnecting an oil well pump driving apparatus from a circuit in the absence of a liquid or the like in a pipeline connected from the pump. A vertical member having a cavity in communication with the interior of the pipeline has vertically spaced differential pressure unit (DPU) inlets. The DPU shuts down the pump motor when there is no liquid in the pipeline.

The Distributed Pipeline

Abstract: Due to the crossbar organization of typical multiprocessors, their cost grows as the square of the number of processors. The distributed pipeline (DP) is a concept which allows the construction and operation of very large multiprocessors; an example having 300 CPU's is described. The DP is an extension of the more traditional pipeline which has been used to implement highly concurrent computers. The DP allows increased concurrency, throughput determined by the average processing time, and the ability to operate at reduced size when one of the elements fails. Each element in a DP can implement a range of functions with little concern for speed matching between elements. The DP is therefore somewhat more general in application than the traditional pipeline, and has certain characteristics which are highly desirable in multiprocessors, e. g., potential for fault tolerance and simple throughput prediction.

Device for positioning a submerged pipeline

Abstract: A device for positioning a pipeline intended to rest on the bottom of the sea or of a body of water. In order to present a resistance to the drifting of the pipeline by the action of cross-currents, the pipeline is provided with a plurality of support members suitably distributed along the pipeline and extending in a direction generally parallel to the vertical plane containing the longitudinal axis of the pipeline. The support members project below the pipeline towards the bottom and are deformable in the vertical plane by the reaction of the bottom on the support members, but are transversely rigid.

A pipeline fast Walsh-Fourier transform

Abstract: The structure for hardware realisation of Fast Walsh-Fourier Transform (FWFT) is presented in this paper. The development of the approach is based on Shanks' algorithm for FWFT and use is made in the realisation of serial storage and simple arithmetic. Two alternative structures are proposed one based on PCM encoding and serial two's complement arithmetic, whilst the other is based on delta-sigma encoding with appropriate arithmetic operations. Comparison of these alternative solutions is given in terms of hardware requirements and the mean square error produced.

Algorithmic and architectural issues related to vector processors

Abstract: This paper considers the increasing impact of computer architecture on algorithm development. After describing the mathematical modeling of parallel/pipeline (vector) processors, the models are used to develop complexity expressions for vectorized solution of certain well known algorithms. These expressions in turn reveal the overhead cost of the vectorization of sequential algorithms. Software and functional characteristics of current vector processors are also discussed.

Pipeline*loading flooring panel

Abstract: PURPOSE:A pipeline-loading and free-to assemble flooring panel designed cap-able of being assembled simply a ntire floor uniformly, and therefore, suitable for providing a floor of good heating efficiency.

Nonlinear filtering with pipeline and array processors

Abstract: Monte Carlo analysis of the combined phase amplitude demodulator problem will be discussed. The effect of machine architectural differences on the nonlinear filtering algorithms will be emphasized. Two machines will be considered; the CDC Star 100 and the Floating Point System's AP120B, which are respectively pipeline and multiprocessor array, in the context of numerical realization of the optimal nonlinear filter for the demodulation problem.

Defect location system for insulated pipelines - has HF cable with meltable metal core surrounding pipeline in spiral winding and connected to electronic system

Abstract: The system is for location of defect sections in an insulated pipeline, e.g. in a pipeline through which a hot fluid flows. The total length of the pipeline is surrounded by at least one spiral wound HF coaxial cable (1) which is laid in contact with the pipeline (7). The HF cable (1) acts simultaneously as a sensor lead, and contains a meltable metal (5) in its interior and is connected to an electronic device which is controlled by impulses send along the cable. If the cable is damaged by excessive heat causing the metal (5) to melt, this is detected and indicated on the electronic device.

Nonlinear Filtering Algorithms for Parallel and Pipeline Machines.

Abstract: : Results are given for the timing of various supercomputers for the problem of phase demodulation. The effect of computer architecture on software development is detailed. (Author)

Transporting method by pipeline

Abstract: PURPOSE:To intend to improve sharply the working efficiency such as reclaiming work by means of applying a combination system of a water power capusule and a slurry

Sectioned thermoplastics drain pipeline - has at least one catch water drain and at least one outlet channel

Abstract: A thermoplastics drainage pipeline is composed of >=2 lengths of pipe has >=1 catch-water drain and >=1 outlet channel. The former has a perforated wall adapted to allow the drainage water to enter, and being connected with the latter via connecting apertures. The lengths of pipe are partitioned by >=1 longitudinally extending dividing walls thereby defining >=1 (upper)catch-water channel at >=1 (lower) outlet channel. The dividing walls adjoins the actual wall of the pipe. The pipe lengths are connected together, with interposition of a spacer gap which acts, at the same time, as a connecting aperture(s). A drain pipeline may be constructed from uniform, standardised, suitably shaped and designed, pipe sections. Each length of pipe is ready-fitted with all components needed to lay a fully operational drainage pipeline.