Showing papers on "Process corners published in 2003"

Timing Analysis in Presence of Power Supply and Ground Voltage Variations

Abstract: Given the sensitivity of circuit delay to supply and ground voltage values, static timing analysis (STA) must take into account supply voltage variations. Existing STA techniques allow one to verify the timing at different process corners which effectively only considers cases where all the supplies are low or all are high. Cases of mismatch between the supplies of driver and load are not considered. In practice, supply voltages are neither totally independent nor totally dependent. In this work, we consider the supply and ground nodes of a logic gate to be either totally independent variables, or to be directly tied or connected to those of some other gate(s) in the circuit. We also assume that the exact supply voltage values are not known exactly, but that only upper/lower bounds on them are known. In this framework, we propose new timing models for logic gates and identify the worst-case voltage configurations for individual gates and for simple paths. We then give an STA technique that provides the worst-case circuit delay taking supply variations into account.

A new low voltage precision CMOS current reference with no external components

Abstract: A novel current reference with low temperature and supply sensitivity and without any external component has been developed in a 0.25 /spl mu/m mixed-mode process. The circuit is based on a bandgap reference (BGR) voltage and a CMOS circuit similar to a beta multiplier. An NMOS transistor in triode region has been used in place of a resistor in conventional beta multiplier to achieve a current which has a negative temperature coefficient and only oxide thickness dependent. The BGR voltage has a positive temperature coefficient to cancel the negative temperature coefficient of the beta multiplier. The simulation results using Bsim3v3 model show max-to-min fluctuation of less than 1% over a temperature range of -20/spl deg/C to +100/spl deg/C and a supply voltage range of 1.4 V to 3 V with /spl plusmn/30% tolerance for all of the used on- chip resistors. The maximum current variation is slightly less than the oxide thickness variation in the process corners.

A low power wideband 2.6 GHz CMOS injection-locked ring oscillator prescaler

Abstract: A high speed and low power prescaler based on an injection-locked ring oscillator is presented. The proposed prescaler uses adaptive biasing to increase the locking range and to eliminate the sensitivity of the locking phenomena to temperature and process variation. The designed circuit can be used in a fractional-N frequency synthesizer. The prescaler operates properly in a temperature range of -20/spl deg/C to +100/spl deg/C and input frequency range from 2.2 GHz to 2.6 GHz in all process corners while its maximum power dissipation is 2 mW at a supply voltage of 1.5 V.

Threshold voltage (Vth), power supply (VDD), and temperature compensation bias circuit for CMOS passive mixer

Abstract: A biasing circuit for a CMOS passive mixer core to stabilize its conversion gain, linearity and noise figure. The RF inputs are fed differentially from the two RF ports, the LO inputs are fed differentially from the two LO ports, and the IF outputs are obtained at the two IF ports. The biasing circuit comprises a reference current derived from the bandgap voltage and a n-channel MOSFET transistor. The conversion gain is stabilized by keeping the Vgs−Vth value of the passive mixer core almost constant at all process corners, temperature and power supply changes. This is achieved by implementing Vs in such a way that it will increase the same amount as VDD decreases, and that Vs will decrease the same amount as Vth increases.

Wafer pattern variation of integrated circuit fabrication

Abstract: A method for manufacturing an integrated circuit on a semiconductor wafer is provided. The semiconductor wafer has complete die and partial die areas thereon. Functional circuit patterns are formed in a plurality of the complete die areas. The thermal absorption properties of the semiconductor wafer are tuned by forming differing patterns in a plurality of the partial die areas.

Semiconductor wafer, semiconductor device, and its manufacturing method

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method which can be utilized without changing a conveying system before and after attachment of a semiconductor wafer with a support plate, and can improve manufacturing efficiency of semiconductor devices, by permitting to reduce finishing precision of the semiconductor wafer and alignment precision between the semiconductor wafer and the support plate. SOLUTION: The semiconductor wafer 1 is arranged such that a step 4 to be separated by removing a rear is formed along a peripheral edge thereof so as to be larger than the thickness of the rear subjected to removal process, and to have a dimension extending outward in the radial direction from a flat surface 1a which is larger than a total of a difference between maximum and minimum finishing tolerance between the semiconductor wafer 1 and the support plate having approximately the same diameter as the semiconductor wafer 1, and a maximum value of alignment error caused at the time of attaching the semiconductor wafer 1 with the support plate. COPYRIGHT: (C)2005,JPO&NCIPI

Analysis and design of level-converting flip-flops for dual-V/sub dd//V/sub th/ integrated circuits

Abstract: This paper investigates the performance and energy consumption of six fully static CMOS edge-triggered level-converting flip-flops (LCFFs) These flip-flops provide the necessary voltage level conversion from a lower to a higher supply without incurring leakage currents in dual-V/sub dd/ systems while maintaining good speed In particular, we propose two novel designs and extend two previous non-level-converting flip-flops to intrinsically perform level conversion In addition, the robustness of the newly proposed LCFFs is investigated based on worst-case process corners as well as power supply noise Results show delay improvement of up to 50% and energy-delay product reductions of 15-50% compared to a conventional level-converting master-slave flip-flop

Semiconductor integrated circuit inspection device and semiconductor integrated circuit inspection method

Abstract: PROBLEM TO BE SOLVED: To easily determine a non-defective/defective of a semiconductor integrated circuit without executing logic simulation and failure simulation. SOLUTION: A plurality of resistors 2 having a prescribed resistance value are connected to a plurality of output terminals OUT of the semiconductor integrated circuit 1, and a prescribed voltage is impressed to the plurality of resistors 2. A prescribed operation pattern signal for inspecting a function of the semiconductor integrated circuit 1 is input to a plurality of input terminals IN of the semiconductor integrated circuit 1. Total of current amounts flowing respectively in the plurality of resistors 2 is measured thereby. The measured total of the current amounts is compared with a normal value in total of current amounts measured using a nondefective sample with a normal operation confirmed preliminarily in place of the semiconductor integrated circuit 1, and the propriety of the normality of the semiconductor integrated circuit 1 is determined based on a result therein. COPYRIGHT: (C)2005,JPO&NCIPI

Using scatterometry to optimize circuit structure manufacturing processes

Abstract: A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. Measurements are taken in accordance with scatterometry based techniques of repeating in circuit structures that evolve on a wafer as the wafer undergoes the fabrication process. The measurements can be employed to generate feed forward and/or feedback control data that can utilized to selectively adjust one or more fabrication components and/or operating parameters associated therewith to adapt the fabrication process. Additionally, the measurements can be employed in determining whether to discard the wafer or portions thereof based on a cost benefit analysis, for example. Directly measuring in circuit structures mitigates sacrificing valuable chip real estate as test grating structures may not need to be formed within the wafer, and also facilitates control over the elements that actually affect resulting chip performance.