Showing papers on "Program counter published in 1985"

Instruction prefetch buffer control

Abstract: An instruction prefetch buffer control (20) is provided for an instruction prefetch buffer array (10) which stores the code for a number of instructions that have already been executed as well as the code for a number of instructions yet to be executed. The instruction prefetch buffer control includes a register (201) for storing an instruction fetch pointer, this pointer being supplied to the buffer array (10) as a write pointer which points to the location in the array where a new word is to be written from main memory. A second register (205) stores an instruction execution pointer which is supplied to the buffer array (10) as a read pointer. A first adder (203) increments the first register to increment the instruction fetch pointer for sequential instructions and calculates a new instruction fetch pointer for branch instructions. A second adder (215) increments the second register to increment the instruction execution pointer for sequential instructions and calculates a new instruction execution pointer for branch instructions. Incrementing of the second register is variable depending on the length of the instruction. A third adder ( 221) is responsive to the output of the first adder and a branch target address to calculate whether the target instruction is contained in the array (10) and, if it is, causes the new instruction execution pointer calculated by the second adder (215) to be loaded into the second register (205).

Apparatus for out-of-order program execution

Abstract: A first load vector instruction signal V1 is read from an instruction buffer into an instruction read register. V1 is decoded and routed simultaneously to scalar and vector processor instruction issue registers. V1 is next routed to a vector instruction stage register and from there to a vector load execution pipe. A second load vector instruction signal V2 proceeds in a similar manner until it reaches the vector instruction stage register and is held there because the vector load execution pipe is busy with V1. A store vector instruction signal S1 proceeds in a similar manner until it reaches the vector processor instruction issue register. S1 cannot proceed further as V2 is queued in the vector instruction stage register. A bypass mechanism includes a bypass test register, a bypassed instruction hold register and a bypass control and sequence logic. S1 is transferred into the bypass test register at each clock cycle. The bypass control and sequence logic initiates a bypass sequence. Under the control of the bypass control and sequence logic, V2 is transferred from the vector instruction stage register to the bypassed instruction hold register. S1 is allowed to proceed to the vector instruction stage register and then on to a vector store execution pipe. V2 is returned to the vector instruction stage register completing the bypass sequence.

Processing device and method

Abstract: @ A device (5) for attachment to a main processor (2) and a method for their operation are disclosed. The device comprises a store (7) for storing secure data essential for the correct action of a computer program, the store being arranged such that the secure data is unreadable by a user, and the secure data defining at least in part one or more steps of the computer program. A subsidiary processor (10) is provided for carrying out the or each step defined by the secure data; and interface means (6) enables data to be received by the device (5) from the main processor (2) and to be transferred from the device (5) to the main processor (2) whereby the device and the main processor together enable the computer program to run. In use, the main processor (2) determines when a step in the computer program is to be found in the device (5) and passes data and a program counter identifying the next step to the device (5). The subsidiary processor (10) carries out the step or steps indicated by the program counter on the transferred data; and passes resultant data and a new program counter to the main processor (2). the new program counter indicating the next step or steps of the computer program to be carried out by the main processor.

Initial setting system

Abstract: PURPOSE:To attain the initial setting without changing an aluminum mask, etc. individually by initializing each part after reading out the initial setting information out of an ROM during a reset period. CONSTITUTION:An initial setting instruction is written on a specific address simultaneously with program writing on an ROM2. When a signal (i) is applied to a reset terminal 11, a program counter 63 is reset. Then the initial setting instruction of the ROM2 is supplied to an instruction register 61 through an internal bus 9. Thus a T/C part 62 including an instruction decoder receives said initial setting instruction and delivers a set signal (b) or a reset signal (c) to an output port 51 and a signal (e) showing the presence of the pull-up resistance or a signal (f) showing the absence of the pull-up resistance to an input port 54 respectively for initialization of both ports.

Tracing system in information processing device

Abstract: PURPOSE:To execute an instruction counter trace and an event trace of only a necessary part by providing a trace control memory which has stored trace information for showing whether a trace is necessary or not, and setting suitably the contents of trace control information. CONSTITUTION:A trace control memory 5 of a trace device 10 receives an address signal from an address bus 9A of a common bus 9. On the other hand, a trace control device 6 receives a control signal from a control bus 9C of the common bus 9. When a prescribed control signal is received, a processor 1 detects a fact that an access of some device or a memory has been started, and in this case, trace control information is read out of the trace control memory 5. Subsequently, in accordance with this trace control information, prescribed information loaded on the common bus 9 is fetched, and control for storing it in a trace information memory 7 is executed.

One-chip microcomputer

Abstract: PURPOSE:To keep the secrecy of the memory contents by having the scrambling so that only a prescribed person can use effectively the read-out contents and using a scrambled address to read out the contents of a mask ROM. CONSTITUTION:An address which is scrambled by a scrambling circuit 5 of a microcomputer 2 is applied to the access of a mask ROM4, and the instruction read out of the ROM4 is sent to a multiplexing circuit 6. The address and the instruction sent to the circuit 6 are delivered by a time division system to undergo a quality check. Therefore it is possible only for a person who knows the relationship between the address produced from a program counter 1 and the address delivered from the circuit 5 to know the relationship between an actual address and its corresponding instruction. Thus the privacy is kept for the memory contents.

The MUSE machine—An architecture for structured data flow computation

Abstract: Computers employing some degree of data flow organisation are now well established as providing a possible vehicle for concurrent computation. Although data-driven computation frees the architecture from the constraints of the single program counter, processor and global memory, inherent in the classic von Neumann computer, there can still be problems with the unconstrained generation of fresh result tokens if a pure data flow approach is adopted. The advantages of allowing serial processing for those parts of a program which are inherently serial, and of permitting a demand-driven, as well as data-driven, mode of operation are identified and described. The MUSE machine described here is a structured architecture supporting both serial and parallel processing which allows the abstract structure of a program to be mapped onto the machine in a logical way.

Data transfer controlling circuit

Abstract: PURPOSE:To omit a conditional branch instruction for waiting for a data transfer, to reduce the number of steps of a program, and to hasten a processing speed by controlling a program counter by a control signal from a controlling circuit. CONSTITUTION:When waiting for an execution of a data transfer of a slave processor, in case of judging the end of the data transfer by a master processor, a control is executed as follows. That is to say, a program counter 1 is controlled by an instruction 5 for transferring a data through an interface register 9, and a program counter control signal 14 from a controlling circuit 13 by which an RQ flag 8 becomes an input signal. As a result, the RQ flag 8 is set, a data transfer is requested to the master processor, and thereafter, a program sequence to immediately before an instruction for transferring a data through the register 9 in the succeeding instruction group is executed automatically. Accordingly, a conditional branch instruction for waiting for a data transfer is omitted, the number of steps of a program is reduced, and the processing speed can be hastened.

A cache-based multiprocessor with high efficiency

Abstract: Shared-memory multiprocessors to support concurrent languages for general-purpose multitasked systems are analyzed. To solve the traditional performance problems caused by memory access latency and conflicts, extensive caching of instructions and data is performed in each processor mode. Caches are private to each processor, and coherence is maintained in hardware between the caches. To maintain a good efficiency, several contexts are resident in each processor. On a miss in the cache, a microswitch to another resident context is operated by changing the program counter and a pointer in the register memory. The instruction set of each processor is RISC-like, so that a microswitch should waste few machine cycles. The proposed system has high efficiency, even when the number of processors increases and when the coherence overhead and conflicts are high. Models are developed to evaluate throughput and efficiency.

Forth-like language microprocessor

Abstract: A language specific microprocessor for the computer language known as FORTH is disclosed. The microprocessor includes four main registers each for holding a parameter; a L or instruction latch register for decoding instructions and activating microprocessor operation; an I or return index register for tracking returns; an N or next parameter register for operation with an arithmetic logic unit (ALU); and a T or top of parameter stack register with an appended ALU. A return stack port is connected to the I register and a parameter stack port is connected to the N register circuit, each have last in/first out (LIFO) memory stacks for reads and writes to isolated independent memory islands that are external to the microprocessor. The respective I, T and N registers are connected in respective series by paired bus connections for swapping parameters between adjacent registers. A first split 16 bit multiplexer J/K controls the LIFO stack for the I and N registers on paired 8 bit address stacks; a second 16 bit multiplexer designates the pointer to main memory with 65K addresses and an adjoining 65K for data. This addressing multiplexer receives selective input from a program counter P, the return index register the top of the parameter stack T and/or the instruction latch L. Movement to subroutine is handled in a single cycle with returns being handled at the end of any designated cycle. Asynchronous microprocessor operation is provided with the address multiplexer being simultaneously set up with an address to a future machine step, unloading from memory of appropriate data or instruction for the next machine step and asynchronously executing the current machine step. A two-phase clock latches data as valid on a rising edge and moves to a new memory location on a falling edge. This two phase clock is given a pulse width sufficient for all asynchronous cycles of microprocessor operations to settle. The microprocessor's assembler language is FORTH and the stack and main memory port architecture uniquely complements FORTH to produce a small (17,000 gates) fast (40 mips) microprocessor operable on extant FORTH programs. Provision is made for an additional G port which enables the current operating state of the microprocessor to be mapped, addressing of up to 21 bits as well as the ability to operate the microprocessor in tandem with similar microprocessors.

Branch destination buffer storage device

Abstract: PURPOSE:To output a correct target instruction train by using the value of a base register and an index register commanded by a branch instruction as one of associative keys in an instruction processing device. CONSTITUTION:A branch destination buffer storage device 102 inputs a register value designated by register designating information in a branch instruction as an associative key through signal lines 104, 106, 110 and 112, and outputs an instruction group containing a target instruction word of its branch instruction to a signal line 118. Accordingly, even in case one branch instruction is made to branch to any one of plural target instructions in the same way as a subroutine return, it can be handled in the same way since the associative key is different.

Program control device

Abstract: PURPOSE:To improve the use efficiency of an arithmetic part by executing control of repeated execution of a program by keeping pace with processing in the arithmetic part. CONSTITUTION:When an instruction code 17 is decoded by a cotrol part 16, a stack pointer 14 is subtracted by ''1'', and the loop numbers contained in the instruction code 17 and values of a program counter 11 are stored in a stack 13 of its address. When an instruction code 18 is decoded by the control part 16, this program control device is operated as shown by b-0, b-1 and b-2 by a loop bit in the instruction code 18 and a result of a decrementer. When an instruction code 19 is decoded by the control part 16, this program control device is operated as shown by c-0 and c-1 in accordance with whether the loop bit is ''0'' or ''1''.

Microprocessor with execution unit independently put into standby condition

Abstract: A microprocessor of CMOS structure which includes at least an execution unit and a control unit including an instruction register adapted to receive and store instructions to be executed by the microprocessor and an instruction decoder receiving the instruction from the instruction register and outputting a control signal. Furthermore, the processor comprises a second instruction decoder receiving at least a portion of the instruction applied from the instruction register to the first instruction decoder so as to supply a standby control signal to the execution unit.

Program test device

Abstract: PURPOSE:To detect accurately a cause of an abnormality with simple constitution and to attain ease of program test by designating a range of addresses where an error is generated and its data range. CONSTITUTION:The range of addresses generating an abnormality is set to an address setting circuit 5 of a program test device and a permissible upper limit value and lower limit value of data registers 3a-3n of a computer 1 are set to a comparison data range setting circuit 6. The value of a counter 2 is read by the 1st register circuit 7 at each write instruction to the registers 3a-3n in synchronizing with the updating of the program counter 2 of the computer 1, and the value of the registers 3a-3n being the range of the address set by the circuit 5 is read in the 2nd register circuit 8 synchonizingly. The contents of the circuit 8 and the permissible value set to the circuit 6 are compared by a comparator circuit 6. The contents of the counter 2 stored in the circuit 7 and the contents of the registers 3a-3n stored in the circuit 8 are displayed on a display circuit 10 depending on the result of comparison of the circuit 9 to ease of the program test.

Method and device for coded data transmission in data processing systems

Abstract: In a data processing system with microprocessors, which are internally organised via data, address and control bus lines and in the central processing unit of which instructions from an instruction register are decoded in an instruction decoder, the instruction decoding is designed to be variable. In particular, several instruction decoding patterns can be programmed in. Each of the instruction decoding patterns can be allocated to an address group. Alternatively, the selection of the instruction decoding pattern can be made dependent on which word of the operation code is currently being processed. A corresponding programmable instruction decoder (9) can be integrated in a microprocessor chip or arranged at least partially outside the processor chip.

Sequence control circuit

Abstract: PURPOSE:To improve the processing efficiency for decoding of an instruction by using the 1st instruction register which stores an instruction for use of an arithmetic unit and the 2nd instruction register which stores an instruction for no use of an arithmetic unit. CONSTITUTION:The instructions are read successively out of the address of an instruction ROM indicated by a program counter PC, then fetched to an instruction register IRO. The output of the IRO is connected to an instruction register IR1, an arithmetic part instruction register ALU-REG and a decoder DEC1 respectively. The DEC1 decodes whether the instruction is equal to an arithmetic instruction or an instruction related to the arithmetic part. If an instruction related to the arithmetic part is decided, an instruction related to the arithmetic part is registered to the register ALU-REG via the IRO. After the instruction is once registered, the number of cycles needed for execution of the instruction is counted by an arithmetic part decoder ALU-DEC. Then the input of the next instruction is inhibited until said number of cycle is counted up.

Data processing unit

Abstract: PURPOSE:To stop either of read/write when they compete with each other by providing an address comparator means comprising an address in plural ports, a gate means gating a write signal and a clock stop means. CONSTITUTION:A cycle clock CYCLK is generated from a clock CLK, fed to an each internal register, which is controlled. A comparator 19 compares an address of the 1st address register 11 and an address of the 3rd address register 13 and a comparator 20 compares an address of the 2nd address register 12 and an address of the register 13. Thus, when read/write are applied to an address of a RAM14 at the same time, since an address of write destination is set to the register 13, an H level signal of address coincidence is outputted from either of the compartors 19, 20. This signal is fed to an inverter 26, the level of a NAND gate 28 goes to an H level, the generation of the cycle clock CYCLK is interleaved once and the operation of the program counter 1 is stopped for one cycle.

Magnetic recording and reproducing device

Abstract: PURPOSE:To vary the tape speed in case an after-program is equal to a tape program and to perform the time correction within said program, by providing an arithmetic means which calculates automatically the delay or gain of time from the broadcast time point of the present program and the end time point of the program. CONSTITUTION:An arithmetic circuit 1 performs an arithmetic of (B-A+C) when the present time point A, the program end time B and the program time C applied to input terminals T1-T3 respectively are supplied. The calculated time is converted into the address value of an ROM by an address converting circuit 2, and the speed set value is delivered from an ROM3 and supplied to a program counter 4 in a servo circuit. For example, the calculated 10 seconds are corrected within 14 minutes and 50sec. In such a case, the counter output is set at 60.66Hz since the oscillation frequency of a reference crystal oscillating circuit 5 is set at 600kHz. Thus the tape speed is incresed by 1.0035. The output of the counter 4 drives a capstan motor 8 through a phase detecting circuit 6 and a capstan drive amplifier 7.

Program debugging device

Abstract: PURPOSE:To elucidate the origin of a branch in case when a branch phenomenon whose origin is unknown appears in some address range of a program by providing plural address designating registers and large or small deciding circuits. CONSTITUTION:As for a value of an address designating register 18, a value which is larger than a value of an address designating register 4 is given. In a debugging mode, a large or smalle deciding circuit 19 subtracts the contents of the register 4 from the contents of a memory address register 3, and outputs ''on'' if the result is positive or ''0''. Also, a large or small deciding circuit 20 subtracts the contents of the register 3 from the contents of the register 18, and outputs ''on'' if the result is positive or ''0''. Outputs of these circuits 19, 20 are inputted to logical circuit 21, and if its result is on, an execution of a program is stopped. A program address of this stop time is not only the contents of the register 3 but also the contents of a program counter 17. In this case, a value of the counter 17 of one instruction before is held is a register 22. In this way, the origin of a branch can be elucidated.

Interruption control method in virtual computer system

Abstract: PURPOSE: To remove the wasteful time due to the break-in of the control program by writing the address of the interruption processing program of the running virtual computer to each entry of the vector table of the control program referred-to by an actual computer beforehand at the time of the occurrence of the interruption. CONSTITUTION: While a user program UP 515 is executed under the operating system OS 506 of a virtual computer VM, the interruption is executed, and then, the hardware of the actual computer BM 501 starts to execute the interrup tion processing. Since the address of the stack 558 of a special control program VMM 502 is indicated by a system stack pointer SSP, the contents of the SSP are re-written to the address of a stack 556 at the dispatching processing, and then, the condition of the program counter IAR of the BM 501, various arithme tic registers and processors is directly saved to the stack 556 in the OS 506. For the new instruction removal of the action of the BM 501, the head address of an interruption processing program 557 of the OS 506 of the VM is set direct ly to the IAR. COPYRIGHT: (C)1986,JPO&Japio

Special Purpose Digital Hardware

Abstract: This paper explores the implementation of special purpose digital hardware devices, using Reed-Solomon decoders as its primary example. A design methodology is presented for implementing “special purpose microprocessors” — microprogrammed devices designed to carry out specific tasks. Several Reed-Solomon decoder designs with differing throughputs and costs are discussed in light of this methodology.

Simulation device of logical circuit

Abstract: PURPOSE:To attain high speed processing by utilizing the result of verification of a low-order logical block to verify the function of a logical block of high- order, thereby decreasing the time required for the verification. CONSTITUTION:The storage content of a circuit state storage device 1 storing the circuit state of a logical circuit to be simulated is fed to an operating device 2 as required. The operating device 2 decodes connecting information fed from a connecting information storage device 3 as an instruction and simulates a logical element. Then the simulation of the gate level is operated sequentially by an instruction counter 4 and an instruction address kew 5. A logical function storage device 6 added thereto stores an output state value to an input state value to the logical block in executing the simulation of the low-order logical block comprising plural logical gates, receives the output of the operating device 2 as an address and returns the corresponding storage content.

Terminal recursive call controlling system of function type machine

Abstract: PURPOSE:To execute a terminal recursive call to each other between a subroutine function and a microroutine function by performing receipt and delivery of a program counter return address CONSTITUTION:When a subroutine function SUBRf1 executes a terminal recursive call to a microroutine function MICROf2, a control is delivered to f0 shown by the value of a program counter PC at the time of resetting from f2, by setting in advance the value of a program counter save PCS to the PC On the other hand, when the MICRO function calls the SUBR function, the SUBR function is started by storing the value of the PC in a PCS area of a stack That is to say, when executing the terminal recursive call, the value of the PC is stored in the PCS area of a dead own frame, and when resetting from the SUBR function f2, the control is delivered to f0 shown by the MICRO function f1 In this regard, the terminal recursive call means to execute a function call by using suitably a frame of the present call origin function

Program starting method

Abstract: PURPOSE:To improve the performance of a computer system by executing a resetting instruction after altering the value of an instruction counter store area in a PSW (program status word) which is shunted when an interruption is produced to the value showing the start address of an interruption processing program. CONSTITUTION:When a study is through with an interruption factor, the contents of an instruction counter store area 2 in a PSW1 which is shunted when an interruption is produced are extracted and pushed into a stack 4 of an interruption processing program 3 to be started. Thus a resetting address to an interrupted program is stored to the stack 4 used by the program 3. Then a start address 5 of the interruption processing program is stored to the area 2. Here the resetting instruction given from the interruption is executed. Thus the PSW1 is stored in the form of resetting from the interruption and branched automatically to the program 3.

Dynamic changing method for memory address generation of data processing system

Abstract: PURPOSE:To attain a dynamic change for the generation of a memory address by changing the generating method of the memory address under the control of a register which can be set with a software instruction. CONSTITUTION:When the address of an instruction word is produced, the contents of an instruction counter 60 which designates the address of an instruction word to be executed are added to the contents of a base field 34 within a resister 30 for instruction segmen describer by an adder 80. When a data address is produced, an address field 51 in an instruction register 50 is added to the contents of an address register 61 by an adder 90. The result of this addition is added to the contents of the field 34 or the contents of a base field 44 in a resister 40 for data segment describer by an adder 110. Thus a data address is produced.

Interruption processing unit

Abstract: PURPOSE:To obtain a return address after execution of interruption processing by using an address generating means of a program counter and a program memory so as to generate a start address of interrupted processing. CONSTITUTION:When an interruption is given at the execution of instruction at 4A(H) during a group of processing using 40(H) as a start address, the content of a program counter 10 is outputted to a bus 22 by using an address output signal 30 to address the program memory, while the content is fed also to AND circuits 40-47 by an interruption reception signal 32. The content of a mask register 11 is fed to the ANd circuits 40-47 by using the interruption reception signal 32 at the same time. The AND circuits 40-47 AND the signals and the result 40(H) is stored in a stack register 12. A return instruction is executed at 1F(H) at the end of interruption. The interruption end signal 33 enters the stack register 12 and the content 40(H) of the register 12 is set to the program counter 10.

Interruption processing method in microcomputer

Abstract: PURPOSE:To increase substantially an interruption level by constituting so that other interruption request can be processed even in case one interruption processing is being executed. CONSTITUTION:A timer interruption routine (TINT) is started, and a value of an accumulator ACC and a value of RAM pointer registers R0, R1 are stored in working registers SAVE3,0,1. Subsequently, a start address (TJMP0) of a timer processing is stored in a register of a program counter stack indicated by existing stack pointers S1, S2 and S3, the stack pointer is brought to increment, and thereafter, a timer interruption is inhibited, and RETR is executed. As a result, it jumps to a start address of a timer processing indicated by PC0-PC11 of the program counter stack. In this case, the RETR instruction is executed already, therefore, an external interruption can be received and processed.

Program evaluating device

Abstract: PURPOSE:To monitor the execution state of a program on real-time basis by varying the execution speed of the program and displaying its in-execution state. CONSTITUTION:A monitor computer 23 is operated in synchronization with output pulses of a pulse generator 21 equipped with an execution speed varying mechanism 22, and a target system 25 is put in operation through an execution computer 24 with an execution command of the specified execution speed of the computer 23; and the contents of a program counter from the computer 24 are fetched by the computer 23 and its execution state is displayed on a display device 26. Thus, the execution state is displayed by using the mechanism 22 at an easy-to-monitor speed.

Program tracing system

Abstract: PURPOSE:To debug easily a program and to reduce the capacity of a memory by adding a step specification signal to a program memory and storing only a step specification signal at a point suddenly changing the order of steps to a trace memory. CONSTITUTION:A program counter 1 in a program tracing system counts up clock pulses CLKs and outputs a step specification signal STP for values increasing sequentially and continuously. The signal STP is added as an address to a memory 2 in which a program is stored and a processor 3 is operated in accordance with respective read steps. The state of the counter 1 is changed by the processor 3 to output an address to be branched. A trace counter 4 counts up the CLKs and applies the counted output COT to a subtractor 5. The subtractor 5 finds out the difference between the specification signal STP and the output COT and a comparator 7 compares the difference with the preceding value. When both the values are dissident, the value of the trace memory 8 is updated to debug the program.