Showing papers on "Rader's FFT algorithm published in 2011"

The Centered Discrete Fourier Transform and a parallel implementation of the FFT

Abstract: This paper describes a novel method for the computation of the Discrete Fourier Transform (DFT). The development of a truly centered DFT is coupled with a method for computing the Centered DFT to provide an FFT that requires no complex multiplications and which allows a highly parallel implementation.

Performances of Texas Instruments DSP and Xilinx FPGAs for Cooley-Tukey and Grigoryan FFT Algorithms

Abstract: Frequency analysis plays a vital role in the applications like cryptanalysis, steganalysis, system identification, controller tuning, speech recognition, noise filters, etc. Discrete Fourier transform (DFT) is a principal mathematical method for the frequency analysis. The way of splitting the DFT gives out various fast algorithms. In this paper, we present the implementation of two fast algorithms for the DFT for evaluating their performance. One of them is the popular radix-2 Cooley-Tukey fast Fourier transform (FFT) algorithm and the other one is the Grigoryan FFT based on the splitting by the paired transform. We evaluate the performance of these algorithms by implementing them on the TMS320C5416 DSP and also on the Virtex-II FPGAs. Finally, we show that the paired-transform-based algorithm of the FFT is faster than the radix-2 FFT; consequently, it is useful for higher sampling rates. We also discuss the performances of TMS DSP and Xilinx FPGAs and tradeoffs.

Offset DMR: A Low Overhead Soft Error Detection and Correction Technique for Transform-Based Convolution

Abstract: A novel concurrent soft error detection and correction scheme is introduced for parallel hardware implementations of transform-based convolution. The proposed technique is based on the structure of radix-2 Fast Fourier Transforms (FFT) of length 2n where n is an integer. The scheme can provide up to 100 percent detection and correction of isolated single soft errors in the convolution at the cost of little more than double the system area, rather than triple, as is required when using conventional Triple Modular Redundancy (TMR).

Comparison of reconfigurable FFT processor implementation using CORDIC and multipliers

Abstract: In this work, two different methodologies for the implementation of a Fast Fourier transform processor: FFT using CORDIC and FFT using Multiplier are investigated. Reconfigurable FFT using radix-2 Decimation in frequency technique is chosen for the comparison. In terms of area and power, both the implementations were analyzed. Coordinate Rotation Digital Computer (CORDIC) is widely used in DSP applications. It utilizes only add and shift operations instead of multipliers. Both CORDIC and multiplier are employed here for twiddle factor multiplication. The experimental result shows that the multiplier based FFT implementation has lower area and power consumption, as compared to CORDIC based implementation.

A New Overlap Save Algorithm for Fast Block Convolution and Its Implementation Using FFT

Abstract: Convolution of data with a long-tap filter is often implemented by overlap save algorithm (OSA) using fast Fourier transform (FFT). But there are some redundant computations in the traditional OSA because the FFT is applied to the overlapped data (concatenation of previous block and the current block) while the DFT computations are recursive. In this paper, we first analyze the redundancy by decomposing the OSA into two processes related to the previous and current block. Then we eliminate the redundant computations by introducing a new transform which is applied only to the current data, not to the overall overlapped data. Hence the size of transform is reduced by half compared to the traditional OSA. The new transform is in the form of DFT and it can be implemented by defining a new butterfly structure. However we implement it by a cascade of twiddle factor and conventional FFT in this paper, in order to use the FFT libraries in PC and DSP. The computational complexity in this case is analyzed and compared with the existing methods. In the experiment, the proposed method is applied to several block convolutions and partitioned-block convolutions. The CPU time is reduced more than expected from the arithmetic analysis, which implies that the reduced transform size gives additional advantage in data manipulation.

A cooley-tukey modified algorithm in fast fourier transform

Abstract: We would like to propose a Cooley-Tukey modified al- gorithm in fast Fourier transform(FFT). Of course, this is a kind of Cooley-Tukey twiddle factor algorithm and we focused on the choice of integers. The proposed algorithm is better than existing ones in speeding up the calculation of the FFT.

Improvement of FFT-based cross-correlation algorithm for PIV

Abstract: An improved fast Fourier transform(FFT)-based cross-correlation algorithm is proposed to solve the computational efficiency problem of cross-correlation in particle image velocimetry(PIV).Based on the decimation in frequency theory,when the overlapping correlation window size is about 50%,the one-dimensional FFT values of overlapping windows are composed of their neighbor sub-window′s FFT values by using the frequency shift instead of implementing FFT and the repeating computation in FFT is greatly reduced.Finally,the proposed method was tested with the real particle images continuously acquired by CCD camera.The experimental results show about 12.25% increase in computational efficiency compared with the traditional method.

Addition Chains Algorithm Based on Fast Fourier Transform

Abstract: Some algorithms for generating addition chains are discussed, Fast Fourier Transform is considered thoroughly, and then a new algorithm based on FFT is proposed to quickly generate addition chains. The new addition chains given by the FFT based algorithm consist lots of multiply 2 operations, which can generate the addition chains at the fastest speed and can make the addition chains shortest. The new addition chain is close to the shortest addition chain. Besides, the FFT based algorithm for addition chains can be parallel implemented to improve its efficiency. More important, this algorithm gives a new direction for the research and application of FFT algorithm.

Optimized iterative WFTA method for the 3780-point FFT scheme

Abstract: In this paper, the classical Winograd Fourier transform algorithm (WFTA) is analyzed in 2-D DFT form. A common method is deduced to build the mapping matrix for the iterative WFTA, which is used to optimize the 3780-point FFT processor in the TDS-OFDM scheme. In this optimized scheme, mapping addresses for the reorder RAMs are replaced by a generator, which saves 181,400 bits of the ROM storage. The analysis and simulation results show that the proposed scheme reduces 45% multiplications in the computational complexity, and it consumes lower hardware resources than the existing designs. The proposed design satisfies the requirement of the Chinese Digital Terrestrial/Television Multimedia Broadcasting (DTMB) standard.

Fixed point FFT algorithm realization in OFDM channel estimation

Abstract: In this paper, four schemes for the fixed point Fast Fourier transform (FFT) algorithm are discussed. Comparisons are made in tradeoff between accuracy and complexity. Several results are obtained through simulation. First, the fixed point schemes given by Welsh and Int-FFT (Integer FFT) scheme by S. Oraintara are compared. Also, the upper bound given by Welsh is tested. Second, based on the comparison, two different methods are chosen for OFDM channel estimation. Our contribution here is that we use two different schemes to perform IFFT and FFT separately. Before being put into implementation, a little change in the fixed-point scheme is made. Last, mean squared errors (MSE) are compared between the float point channel estimation algorithm for OFDM systems and its fixed-point counterpart. The simulation result shows that these two performances are almost the same above 14-bit data quantization. In the paper, accuracy is the main concern and radix-2 is in use.

A VLSI architecture for real-time signal FFT based on pipelined processing element

Abstract: In this paper, a VLSI architecture for real-time signal FFT based on pipelined processing element (PE) is proposed. The proposed architecture suits to FFT/ IFFT and supports input/ output simultaneously. In the system a 2 MN point FFT can be computed by 2 M point row-wise FFT followed by 2 N point column-wise 2-D FFT. By this way long length FFT is divided continuously until it could be conquered by some short length processing elements (PE). The proposed pipelined PE architectures are based on short length FFT algorithms used in WFTA, so multiplier number in PEs is minimal. A 1024-point complex FFT is implemented in XC2VP30-7 FPGA board based on the VLSI architecture. Result shows that latency between input and output is about 3300 clock cycles, and the computation time for real-time signal FFT is minimal compare to recent research. The proposed architecture also has flexible configuration for different point FFT.

A Heuristic Description of Fast Fourier Transform

Abstract: Fast Fourier Transform (FFT) is an efficient algorithm to compute the Discrete Fourier Transform (DFT) and its inverse. In this paper, we pay special attention to the description of complex-data FFT. We analyze two common descriptions of FFT and propose a new presentation. Our heuristic description is helpful for students and programmers to grasp the algorithm entirely and deeply.