Showing papers on "Registered memory published in 1981"

WSCLOCK—a simple and effective algorithm for virtual memory management

Abstract: A new virtual memory management algorithm WSCLOCK has been synthesized from the local working set (WS) algorithm, the global CLOCK algorithm, and a new load control mechanism for auxiliary memory access. The new algorithm combines the most useful feature of WS—a natural and effective load control that prevents thrashing—with the simplicity and efficiency of CLOCK. Studies are presented to show that the performance of WS and WSCLOCK are equivalent, even if the savings in overhead are ignored.

Shared memory computer method and apparatus

Abstract: A shared memory computer method and apparatus having a plurality of sources, a memory manager, and memory units in which the memory locations of data items are randomly distributed. The memory manager includes a translation module for locating data items in the memory units and a temporary storage buffer for storing at least a portion of messages between sources and the memory units with respect to data items.

Display system with multiple scrolling regions

Abstract: A data display and management system includes a microprocessor whose functions are implemented by instructions in data from a directly connected main memory. A mass data storage memory is connected to the main memory and has permanently stored instructions therein for the microprocessor. A display control system which operates asynchronously with the microprocessor includes a display controller, display memory, character memory means, and a visual character attribute generator. By linking one or more row attribute bytes, or pointers, to each row of characters stored in the display memory the display controller performs character and row manipulation on a display device without transferring whole blocks of data in the display memory. Multi-region display segmentation into horizontal and vertical split regions, smooth or discrete scrolling of individual regions, and various editing functions are achieved by modifying the associated display memory pointers.

Device for the use of and easily carried by an individual

Abstract: A device for the use of and easily portable by an individual, consisting of a main memory, a microprocessor, a keyboard for the control of the microprocessor, etc., and at least one accounting memory and a display. Operation of the keyboard in a pre-determined fashion will cause the microprocessor to transfer one or more units of information from the main memory to at least one accounting memory. The point in time at which this transfer is made directly or indirectly (for example via internal delay circuits) may be determined by the individual. The number of information units to be transferred is determined by operating the keyboard in a certain, preferably combinatory fashion. Each information unit or group of units which is transferred from the main memory to the accounting memory by operating the keyboard in some other, certain, preferably combinatory fashion will either be given a certain address code or will be allocated to a specific accounting memory.

Signal transfer timing control using stored data relating to operating speeds of memory and processor

Abstract: A memory controlling apparatus retains time information prepared based on performance of a memory and a processor, and determines timing of signal exchange between the memory and the processor based on the time information. An access time to the memory is reduced while maintaining a flexibility to a change of the access time due to increase of memory capacity or reconfiguration of the memory.

Memory system employing mostly good memories

Abstract: A memory system is described which employs a plurality of "mostly good" memory chips. A redundant memory chip is used to store data designated to the defective locations in the mostly good memories. In one embodiment a PROM is programmed to recognize the addresses of the defective elements and to cause the redundant memory to be selected. In another embodiment, a content-addressable memory is employed to provide a new address in response to the addresses of defective elements in the mostly good memories.

Memory protection system

Abstract: A memory protection system includes an auxiliary power supply source for maintaining information stored in a random access memory when the main power supply is terminated. When the main power supply voltage level becomes lower than a preselected level, a detection unit develops a control signal for applying a disabling signal to a chip selection terminal included in the random access memory, whereby a load such as a central processor unit connected to the random access memory is electrically disconnected from the random access memory to minimize the power dissipation.

Redundancy scheme for an mos memory

Abstract: An MOS memory has a main array of memory cells (10, 12) and a plurality of spare memory cells (22, 24). Typically, each memory cell is tested for operability by a conventional probe test. A redundancy scheme is provided for substituting spare memory cells for memory cells found to be defective. An on-chip address controller (38-50) responds to the probe test finding a defective cell by permanently storing and rendering continuously available a fully asynchronous electrical indication of the address of the defective cell. The address controller (38-50) compares its stored data with memory cell information received during normal memory operation, and generates a control signal indicative of the receipt of an address which corresponds to a defective cell. A spare cell selector (106, 108) responds to the control signal by electrically accessing a spare memory cell and by prohibiting access of the defective memory cell.

Digital data processing system having object-based logical memory addressing and self-structuring modular memory

Abstract: A digital computer system in which the memory is structured into objects, which are blocks of storage of arbitrary length, in which the data items are accessed by specifying the desired object and the desired data item's offset into that object. The memory controls accommodate any number of memory arrays of any size, automatically transforming the addresses to present the appearance of a single unified memory bank.

Memory system having an alternate memory

Abstract: A memory system having both a primary memory and an alternate memory. The alternate memory stores data to be substituted for data stored at memory locations in the primary memory that have defective cells. The alternate memory includes a byte memory and a bit memory. The byte memory stores bytes of data that are to replace bytes having multiple bit errors in the primary memory. The bit memory stores bits to replace single bits in any byte in the primary memory that has a single bit error. A mapping memory controls access to the primary memory and the alternate memory. The memory devices in the primary memory have either all row defects or all column defects in order to reduce the size of the mapping memory.

Automatic memory module address assignment system for available memory modules

Abstract: An automatic Memory Module sensing and Memory Module address assignment system during an initializing sequence is described. Each Memory Module has a memory assignment register associated therewith, and all memory assignment registers are initialized to an illegal Memory Module address. The interlock and switch signals are sequentially evaluated under control of a scan counter and decoder. A memory assignment counter is utilized to develop sequential Memory Module addresses and is advanced for each Memory Module found to exist in the system. The memory assignment register for the Memory Module under consideration is set to the address specified in the memory assignment counter if the Memory Module is determined to be present, or is left storing the illegal code if the Memory Module being considered is not present in the system or is switched off. A memory capacity counter is advanced for each Memory Module found to exist in the system, and upon completion of the initializing sequence, provides signals indicative of the total Memory Module capacity of the system. In the event no memory is available, a signal indicating that status is provided to the data processing system. Upon completion of the evaluation of all Memory Modules in the system, the automatic memory assignment sequence is terminated and memory accessing can commence, with Memory Modules being accessed by comparison of applied Memory Module address signals to the contents of the memory assignment registers. Mode selection provides alternatively for assignment of Memory Module addresses sequentially for individual Memory Modules in the Normal Mode, or for pairs of Memory Modules in the Page Mode.

I/O Adapter with direct memory access to I/O control information

Abstract: A data proessing system includes a processor, a memory, a direct memory accessing (DMA) control unit and an input/output adapter. A memory area of a given capacity is reserved in the memory for storing control information transferred between the processor and the adapter. For transfer of the control information, the adapter accesses the control information stored in the memory area through direct memory accessing under control of the DMA control unit while the processor can make access to the control information through a memory read/write command. By storing at the predetermined area of the memory the control information transferred between the processor and the adapter, the quantity of hardware and the number of IC's required for implementing the adapter can be significantly reduced. Conflicting access requests to the main memory area by the processor and adapter are prevented through time-division control of the memory bus.

Memory patching system

Abstract: A memory patching system which transfers permanent-type information in a read-only memory (ROM) to a random access memory (RAM) and modifying contents of the RAM in accordance with patch information in an eraseable programmable ROM is disclosed.

Pause apparatus for a memory controller with interleaved queuing apparatus

Abstract: A data processing system includes a plurality of memory command generating units which connect to a common bus network with a number of memory subsystems. Each subsystem includes a controller which controls the operation of a number of memory module units and includes a number of queue circuits for storing memory requests to be processed. The memory controller further includes control apparatus connected to monitor bus activity. In response to certain bus activity conditions occurring during multiword transfer operations, the control apparatus operates to lengthen the time between successive multiword transfers of data to the bus so as to ensure that new requestors having lower priorities than a memory controller gain access to an available queue notwithstanding the amount of bus delay incurred in transmitting their memory requests.

Direct memory access control apparatus

Abstract: A direct memory access control apparatus performs direct data transfer between a memory and an input/output controller in a data processing system. When the system is placed in a direct memory access mode upon receipt of a direct memory access request from the input/output controller, a data bus connected between the input/output controller and the memory is separated from a central processing unit by means of a data bus separating circuit, and an address bus of the memory is also separated from the central processing unit by means of an address bus switch circuit. The address bus of the memory is connected to a direct memory access controller by means of the address bus switch circuit. Therefore, the memory is addressed by the direct memory access controller through the address bus while the data is directly transferred between the memory and the input/output device through the data bus.

ROM security circuit

Abstract: A control circuit to disable the operation of a semiconductor microprocessor memory device in the event of an unauthorized attempt to access the memory. A logic circuit generates a control signal in response to receiving a predetermined binary bit pattern of a plurality of chip select signals. The control signal enables the memory device for operation. If the binary bit pattern is not presented, the memory device is disabled for operation.

Non-volatile memory system for intelligent terminals

Abstract: An intelligent terminal comprising a first memory system (bubble memory) for storing data including a plurality of function programs; a second memory system (static RAM) and a processor operatively coupled to the static RAM to execute instructions therefrom at high speeds. A keyboard is used for selecting a function program to be executed and a direct memory access controller is used for transferring data, including a function program which is selected by the keyboard, from the bubble memory to the static RAM to enable the processor to execute the selected function program. A comparator is used for determining the end of a selected function program, and a static scratch pad RAM is used to store changes made in data to be returned to the bubble memory.

Semiconductor memory formed of memory modules with redundant memory areas

Abstract: A semiconductor memory has a plurality of modules or boards each with a plurality of memory integrated circuits and redundant memory areas. For receiving of information for replacement circuiting of faulty bit locations in a memory circuit with redundant memory areas, a volatile auxiliary memory is provided in the memory circuit. Each structural unit, which is easily exchangeable in the course of maintenance jobs which encompass a plurality of memory circuits such as a printed circuit board, has associated with it a programmable non-volatile read-only memory for receiving the replacement circuit information for all memory circuits which are combined in the structural unit. The programming of the read-only memory preferably proceeds during testing of the structural unit.

Calculator with constant memory

Abstract: A calculator having constant memory utilizing a classical CMOS metal gate process, a low power microcomputer with on-chip and external constant memory capability. Incorporation of a switched negative voltage and a non-switched negative voltage to the appropriate P (-) wells enables the power hungry clocked logic to be turned off while power is maintained on the internal static RAM, on the digit latches, and on the R-lines which connect to both the internal and external RAM. Thus, semi-non-volatile memory (constant memory) capability may be achieved with a low standby current.

Electron beam pattern generation system

Abstract: Bit pattern data stored in an external memory unit (8) is read out under the control of a microprocessor (9) for being compressed in a data compressing unit (10) and then stacked in a memory unit (30). At the time when storing data in the memory unit (30), all the stripe data constituting one chip frame are written in a state capable being made high speed sequential access to at the time of the read-out without need of dividing a memory bank into portions for the individual stripes but by continuously using the address space covering the entire memory areas. This is effected by a memory management unit and a memory module management unit provided in the memory unit (30).

CRT Refresh memory system

Abstract: A logic memory control system for accommodating plural read/write requests to a video terminal display memory is provided without the need for multiplexing common busses shared by the video terminal logic devices accessing the display memory, or for compromising video terminal data transfer rates.

Memory protection circuit for an electronic postage meter

Abstract: An electronic postage meter includes a memory protection circuit. The memory protection circuit prevents the inadvertent writing of spurious data into memory locations in the nonvolatile memory during a power down cycle. The memory protection circuit works in conjection with a WRITE voltage terminal associated with the nonvolatile memory. Means couple a first voltage source providing a predetermined polarity voltage to the WRITE voltage terminal when a predetermined power condition exists such that the nonvolatile memory is enabled to have data written into memory locations. When the predetermined power condition does not exist, the means utilize a second different voltage source to change the voltage level at the WRITE voltage terminal to insure that data is not written into the memory locations.

Microprogrammed control unit with multiple branch capability

Abstract: A microprogrammed control unit with multiple branch capability comprises in addition to a control memory, a first auxiliary read/write memory (21) having low parallelism and a second auxiliary read/write memory (30) having high parallelism. The reading of a microinstruction from the control memory also causes the reading of an information from the first auxiliary memory, such information being used to address the reading of the second auxiliary memory. The information read out from the second auxiliary memory specifies jump conditions (JC1, JC2, JC3) to be examined and jump addresses (JA1, JA2, JA3) and extends the information contained in the microinstruction read out from control memory. Thus it is possible to associate jump (or branch) microinstructions to operative microinstructions and particularly multiple branch microinstructions to curtail the design time of the microprogram and the control memory size devoted to store them. A priority network 40 coupled to the second auxiliary memory determines the priority to be followed during the concurrent examination of several jump conditions and selects the jump address among several possible addresses according to the highest priority verified jump condition.

Data processing system having interlinked slow and fast memory means

Abstract: A data processing system having a large slow main memory and having a small fast memory is disclosed with means for allowing slow memory calls to fast memory routines and means for allowing returns from programs executing in the fast memory so as to return to program execution in the slow main memory. Also disclosed is circuitry for selectively deactivating the main memory and for selectively activating the fast memory responsive to particular ones of data signals output from the main memory, and means for selectively deactivating the fast memory and for selectively deactivating the main memory responsive to predefined ones of data signals output from the fast memory, thereby allowing program calls embedded in the slow main memory to transfer execution control to the fast memory, and providing retransfer of execution control from the fast memory to the slow main memory in response to a RETURN code embedded in the fast memory. Thus, memory size and speeds may be selectively ratioed to obtain higher overall data processing system throughput.

Parasitic memory expansion for computers

Abstract: A memory expansion circuit for expanding computer memory capacity requiring a minimum of alterations to the host system is disclosed. The memory expansion circuit is parasitic in that it fully exploits address lines, data input and output lines, and control lines already available in the existing host computer system, and it is suitable for use with both static and dynamic memory devices. In a preferred embodiment, a bank of memory devices which responds to a single memory read or write operation in the host computer system is removed, and the parasitic memory circuit containing a number of banks of memory devices is inserted in its place thereby providing a software-selectable number of memory banks to replace the one removed. The method is particularly adaptable for use with contemporary 8-bit microprocessors and especially to systems which are not built around a buss architecture.

Programmable peripheral processing controller with mode-selectable address register sequencing

Abstract: A peripheral processing controller controls time-shared access to a memory by specialized peripheral devices The specialized peripheral devices process data independently of a central processor that simply supervises the system The peripheral processing controller uses predetermined modes of memory space allocation for the various peripheral devices A memory address register in the controller is assigned to each peripheral device In addition, each MAR has one or more predefined modes of memory space allocation and, when active, controls memory access for its assigned peripheral device The modes also define the size of the block of space allocated and whether memory access scrolls through various blocks of space or jumps between blocks of space The controller also detects when a peripheral device has consumed all the space in a block Further, for those MAR's having more than one mode of space allocation, the controller selects the mode appropriate for the peripheral device requesting access to the memory

Semiconductor IC memory

Abstract: Disclosed is a semiconductor IC memory which has memory cells for storing given data; data lines coupled to the memory cells for transferring data stored in the memory cell; decoders having a sense point and coupled to the memory cells and data lines, for selecting one of the memory cells to couple the selected memory cell with the sense point, the potential of the data line coupled to the selected memory cell being changed with the stored data of selected memory cell; and a sense amplifier coupled to the sense point for sensing the stored data of selected memory cell and providing a read out data corresponding to the sensed stored data. Each of said memory cells has a predetermined threshold level which determines the sense point potential. The predetermined threshold level is selected from four fixed levels. The sense amplifier includes comparators coupled to the sense point for comparing the sense point potential with given comparison levels and providing a comparison result corresponding to the predetermined threshold level; and a selection logic coupled to the comparators and responsive to the logical state of comparison result, for providing an output corresponding to two bits of binary data stored in the selected memory cell and used as the read out data.

Communication line adapter for use with a communications controller

Abstract: A line adapter for permitting the transfer of information between terminals and a bus connected to the central control unit CCU of a communications controller. The line adapter includes a microprocessor associated with a control memory and a scanner. A random access memory is split into zones, one zone being assigned to each line. During an initiating phase, the zones are personalized under the control of the microcode by sending initiating parameters (which are characteristics of the lines) to the memory, through an asynchronous path bus and external registers. Exchanges of temporarily-stored data between the CCU bus and the lines are carried out through cycle steal operations between the control memory and the random access memory.

Buffer memory controlling system

Abstract: PURPOSE: To perform assured buffering of data with reduced memory capacity, by dividing a shared memory into plural numbered memory blocks and controlling the using conditions of the divided memory blocks with plural register memories which are provided separately. CONSTITUTION: A processor 1 is started and divides the storage region of a shared memory 2 into plural memory blocks. A serial numbers are added to each divided memory block, and these block numbers are registered to an idle block register memory 3. Wen a serial-parallel converting part 7 receives data from another communication controller, the converter 7 extracts the idle block number out of the memory 3 and stores successively the received data underwent a serial-parallel conversion to the memory blocks in the memory 2 which corresponds to the block number. Then the numbers of the used blocks are registered to a received data storing block register memory 6 at a time point when a series of data reception is over. COPYRIGHT: (C)1983,JPO&Japio

Linear micro-sequencer for micro-processor system utilizing specialized instruction format

Abstract: A microprocessor system comprising an arithmetical logic unit, a program memory and an external memory, memory address means (including a program counter and a memory reference register) for addressing either the program memory or the external memory. The microprocessor is sequenced by a linear sequencing circuit which can use different size plug-compatible PROMs. An instruction register receives instructions from either program memory or external memory along an instruction bus, which instructions are conveyed via a memory operand register to the arithmetic logic unit. The program memory is provided with a specialized instruction word format. The instruction word format provides: a single bit field for selecting either the program counter or the memory reference register as the source of memory addresses; it provides a function field which defines the route of data transfers to be made; and provides a "source and destination" field for addressing selected source and destination locations.