Showing papers on "Residue number system published in 1979"
TL;DR: A numerical optical processor is described that performs operations in residue arithmetic that leads directly to novel residue adder and decimal/residue/decimal converter designs, which are described and experimentally demonstrated.
Abstract: A numerical optical processor is described that performs operations in residue arithmetic. The position coding used to represent decimal and residue numbers allows one to describe the various conversions and operations in a correlation formulation. This description of residue arithmetic leads directly to novel residue adder and decimal/residue/decimal converter designs, which are described and experimentally demonstrated. The accuracy, dynamic range and space bandwidth of an optical residue arithmetic processor are also discussed.
77 citations
TL;DR: In this paper, the implementation of a fast Fourier transform (FFT) structure using arrays of read-only memories is considered, where the arithmetic operations are based entirely on the residue number system.
Abstract: This paper considers the implementation of a fast Fourier transform (FFT) structure using arrays of read-only memories. The arithmetic operations are based entirely on the residue number system. The most important aspect of the structure relates to the scaling arrays, which are required to prevent overflow. Because of the limitations of the number system, scaling factors have to be chosen on an a priori basis. This paper develops optimum procedures for choosing both scaling factors and the position of scaling arrays in the structure. Some examples are presented relating to the filtering of speech via a convolutional filter structure.
42 citations
01 Apr 1979
TL;DR: Using the Residue Number System (RNS) as a basis for the hardware construction, two different hard-ware structures are discussed for implementing NTTs over a direct sum of Galois Fields GF(m i 2), offering trade offs between speed of operation, and cost.
Abstract: Using the Residue Number System (RNS) as a basis for the hardware construction, two different hard-ware structures are discussed for implementing NTTs over a direct sum of Galois Fields GF(m i 2). The first structure uses arrays of read only memories and the second uses arrays of microprocessors; in particular, single chip microprocessors are proposed. The two techniques offer trade offs between speed of operation, and cost. Using the RNS, rather than conventional binary arithmetic, allows more flexibility in the choice of the generator, α, and consequently more flexibility in allowable transform parameters. A selection of parameters, for the two realizations, are discussed when the Galois Field of m i 2elements is a finite field of Gaussian or quadratic integers.
7 citations
22 Oct 1979
6 citations
TL;DR: Consideration is given to the suitability of microprocessor systems for the fast implementation of number theoretic transforms (n. t.t.s) and of how modular arithmetic may efficiently be performed using microprocessors.
Abstract: Consideration is given to the suitability of microprocessor systems for the fast implementation of number theoretic transforms (n.t.t.s). Fast-multiply instructions available on some microprocessors, or the use of external multipliers, relax the basic constraints on the choice of a particular n.t.t. A search was made for suitable moduli which allow fast computation of n.t.t.s using Winograd's algorithm. The search was extended for other moduli which allow increased dynamic range when combined using the Chinese remainder theorem. Finally, a description is given of how modular arithmetic may efficiently be performed using microprocessors
6 citations