Showing papers on "Serial port published in 1995"

FPGA with parallel and serial user interfaces

Abstract: A configuration structure for a field programmable gate array (FPGA) allows a user to reconfigure or partly reconfigure the FPGA from within the FPGA, allows an addressable configuration memory to be addressed in parallel through a set of address and data or through a serial interface. Signals such as chip-enable and other control signals can be modified by user logic so that data loaded through a serial interface pin is entered into an addressed portion of configuration memory. The configuration memory programs not only the internal circuitry accessed by the user but also a programmable switch for directing signals between external pins, configuration memory control lines, and a serial data interface. Providing both parallel and serial interfaces allows a programmable switch which is initially configured to connect its related pad or pads to configuration control lines such as a chip enable line or a serial data input line to later be configured to connect an internally generated signal or signals to the line or lines and thus override any external signal which would have been connected to that line or lines.

Data processing circuits and interfaces

Abstract: An integrated circuit contains (102) a microprocessor core (100), program memory (104) and separate data storage (106, 108), together with analogue and digital signal processing circuitry (110). The ALU (302) is 16 bits wide, but a 32-bit shift unit (312) is provided, using a pair of 16-bit registers. The processor has a fixed length instruction format, with an instruction set including multiply and divide operations which use the shift unit over several cycles. No interrupts are provided. External pins of the integrated circuit allow for single stepping and other debug operations, and a serial interface (SIF) which allows external communication of test data or working data as necessary. The serial interface has four wires (SERIN, SEROUT, SER-CLK, SERLOADB), allowing handshaking with a master apparatus, and allowing direct access to the memory space (104-110) of the processor core (100), without specific program control. Within each processor cycle, the processor circuitry is divided into plural stages, and latches are interposed between the stages to minimise power consumption.

Distributed disk array architecture

Abstract: A RAID-compatible data storage system which allows incremental increases in storage capacity at a cost that is proportional to the increase in capacity. The system does not require changes to the host system. The control and interface functions previously performed by a single (or redundant) central data storage device controller are distributed among a number of modular control units (MCUs). Each MCU is preferably physically coupled to a data storage device to form a basic, low-cost integrated storage node. One of two bus ports interfaces an MCU with the host computer on a host bus, and the other bus port interfaces an MCU with one or more data storage devices coupled to the MCU by a data storage device bus. The serial interface ports provide a means by which each of the MCUs may communicate with each other MCU to facilitate the implementation of a memory array architecture. The entire data storage array may appear as a single device capable of responding to a single identification number on the host bus, or may appear as a number of independent device. A controlling MCU receives a command and notifies the other MCUs that are involved in a read or write operation. Control of the host bus is transferred from one MCU to the next MCU in sequence so that the data is received by the host computer, or written to each data storage device, in the proper order.

System level functional testing through one or more I/O ports of an assembled computer system

Abstract: A test apparatus and method for fully testing the functional aspects of a computer system at the system level through one or more of its I/O ports. A test system is connected to an externally available I/O port of the computer under test for accessing its system ROM and a jumper is installed on the computer under test to disable its system ROM. The jumper also bypasses the PCMCIA controller, if necessary, to provide the test system direct access to the I/O port and thus the system ROM. The computer under test is booted from diagnostic test code stored in memory of the test system, where the diagnostic test code has complete control and performs a series of tests on the computer under test. Other I/O ports of the computer under test, including its serial ports, parallel port, keyboard and mouse ports, video port and a docking port may also be connected to the test system, if desired. Certain portions of the diagnostic test code may be downloaded into video RAM of the computer under test and executed sequentially. Also, a communication protocol may be established between the host computer and the computer under test so that the host computer can control initiation and monitor status of each test routine.

Method and apparatus for displaying module diagnostic results

Abstract: A reliable diagnostic system for running power-up diagnostics, displaying power-up diagnostic results, and retaining a power system status history. First, a method of testing a processor module in a computer system is provided. A processor including a serial port reads processor module diagnostic test instructions from a PROM in a serial line controller through the serial port by way of a serial bus in response to power-up reset instructions. Next, a reliable connection of a serial control bus to the modules is provided. Accordingly, backplane connectors are provided including wide signal conducting elements having multiple solder connection points to the modules and backplane. The serial control bus is electrically connected to each module through the multiple connection points of these signal conducting elements. Also, an apparatus and method for indicating module failures in a computer system is provided. A console panel is provided in the computer system comprising LED's visible to the user, each LED corresponding to a particular module. Any LED which remains lit indicates the failure of the corresponding module. Finally, a method and apparatus is provided for maintaining a power system status history. Status indicators corresponding to various environmental conditions in the system are supplied. When any status indicator changes value, the status indicators are stored in a non-volatile memory. In the event of a system shutdown, the nonvolatile memory then retains a status history representing the environmental changes prior to shutdown.

Distributed environmental process control system

Abstract: A process control system includes a high speed serial backbone communications network, interconnecting a plurality of microprocessor based nodes that each act as the master to a high speed serial branch network comprising device controllers, such as air flow valve controllers and transducers. The primary network may operate in a time division multiplex mode whereby a node acting as a synchronizing station periodically issues a synchronizing signal that commands each node to execute a branch network control sequence, during which each node gathers and operates upon data it collects from the device controllers within its branch network, and issues commands based thereon to the branch network. An ensuing communications sequence also triggered by the synchronizing signal enables each node on the primary network to transmit a command or a response to any other node and, through such other node, to any device controller in any branch network of the system. Serial ports on each node permit user access from any node on the primary network to any other point on the system for purposes of monitoring and control. Serial ports on each device controller permit user access to local device parameters.

Video signal reproducing apparatus

Abstract: In a video reproducing apparatus, operating devices and recording devices are connected with a simple structure to record game information while operating the game, and a plurality of small capacity of external secondary memory means can be used as a large capacity of external secondary memory means. The main body of the video game machine is connected to a plurality of the operating devices with a serial interface so that serial data is communicated bidirectionally in accordance with a predetermined communication procedure while at the same time connecting recording devices to the serial interface respectively corresponding to a plurality of operating devices to allow the main body of the game machine to write predetermined data into and read it from recording devices in accordance with a communication procedure. Moreover, the communication controller connected to the main bus to which the central processing unit of the main body of the machine is connected and a plurality of card connectors namely card slots where memory cards connected to the main bus via the communication controller are attached to or detached from freely are provided, and each card slot is independently controlled by the central processing unit via the communication controller to control the writing and/or reading of data extending over the plurality of external secondary memory means.

Programmable lighting control system for controlling illumination duration and intensity levels of lamps in multiple lighting strings

Abstract: A programmable lighting control system for advertising, decorative, artistic, and Christmas lighting applications, consists of a standalone controller, an optional power booster device, and a personal computer compatible software program. The controller receives power via a standard AC outlet receptacle and includes: a plurality of AC output receptacles for connection to either series or parallel connected Christmas tree type lights or the like; a micro-controller to provide timing and control signals that are applied to solid state switching devices to drive the outlet receptacles; a non volatile memory to store custom user defined lighting sequences; a rotary, switch to enable the selection of either pre-programmed sequences or user defined sequences; and a serial communication port. The personal computer compatible software program enables the user to create custom lighting sequences, which can be downloaded to the light controller non volatile memory via the serial port. The optional power booster device can be used to increase the output power capability of each of the individual controller output circuits.

Computer to fieldbus control system interface

Abstract: An interface device for interfacing a computer to a Fieldbus control system thereby allowing the computer to configure, control, and monitor components such as sensors and actuators which are coupled to the Fieldbus. The interface device connects to a serial port of the computer and to a Fieldbus, providing the necessary formatting of data and conditioning of signals exchanged between the Fieldbus and the computer. The interface device is powered entirely or partially from the computer via the serial port and thus does not further load a Fieldbus to which it is connected. The interface device is also portable and is thus well suited for interfacing a portable computer to a Fieldbus system in the control room or the field, e.g., close to the Fieldbus components to be monitored or controlled.

Method for the cyclic transmission of data between at least two control devices with distributed operation

Abstract: A method for periodic transmission of data between control devices (10, 11, 12) interconnected via a serial bus (20) is provided, particularly for the transmission of synchronization data. The control devices (10, 11, 12) each have a serial interface (17,17'17") and an arithmetic/control unit (15,18). Data are provided for transmission by the arithmetic/control unit (15, 18) of the control device transmitting the data and are included in a message sent over the serial bus (20). To this end, a transmission job for transmitting the message is provided to the serial interface (17) of control device (10) transmitting the message which controls the transmission. However, this occurs so that, when transmitting the message, use is not made of the data provided at the instant of providing the transmission job, but instead of updated data provided by the arithmetic/control unit in the interim since the instant of giving the transmission job. Moreover, advantageous bus subscriber stations for use in the method presented are also proposed.

A Low-power Wireless Microinstrumentation System For Environmental Monitoring

Abstract: This paper reports a hybrid microinstrumentation system that includes an embedded microcontroller, transducers for monitoring environmental parameters, interface/readout electronics for linking the controller and the transducers, and custom circuitry for system power management. Sensors for measuring temperature, pressure, humidity, and acceleration are included in the initial system, which operates for more than 180 days and dissipates less than 700/spl mu/m from a 6V battery supply. The sensor scan rate is adaptive and can be event triggered. The system communicates internally over a 1MHz, 9-line intramodule sensor bus, and outputs data over a hardwired serial interface or a 315MHz wireless link. The use of folding circuit platforms allows an internal system volume as small as 5cc.

Opto-electric golf club swing sensing system having vertically offset sensors

Abstract: A video golf swing sensing system responsive to a user swinging a golf club provides inputs to a video golf game operating on a personal computer having a monitor, a microprocessor, and a serial port. The sensing system is mounted on a pad and includes linear arrays of photodetectors and LED for detecting a club head parameter by sensing light reflected off the club head. A microcontroller processes the parameter data into a form required by the personal computer. An input cable coupled between an output of the microcontroller and the serial port transmits the information to the personal computer to provide the golf game information to determine a corresponding ball path in the video game. The arrays are recessed beneath a shield to facilitate reflection of light from the sources to the detectors within openings in the shield while excluding external light.

Integrated circuit for identifying an item via a serial port

Abstract: Coin-shaped one-wire communication modules with a flange for mounting convenience may be attached to contact extensions on items such as work totes for ease of communication A host computer can keep track and locate multiple items which have mounted communication modules with use of a single data line and a single ground line for all of the modules

Method for autonomously transferring code to a computer without accessing local memory by the central processing unit

Abstract: In a computer-driven device, a start-up mode after reset is provided whereby boot-up instructions are by default always accepted directly from an external source. The device may comprise a gate array (GA) which is connected directly via a serial port to a receiving or input device, to receive program code for transfer directly as instructions to a microprocessor-type central processing unit. The central processing unit is part of a computer controlled device containing a microprocessor, memory (a RAM), and typically a bulk erase flash memory device, the flash memory device being unprogrammed when the computer controlled device is fabricated originally. When the computer controlled device first powers up, a special mode of operation ensues in which the gate array directly monitor bits received via the serial port from the input device and shifts them into a local register from which bytes or words are loaded directly into the CPU as instructions. A boot sequence is thereby accepted in this manner to load random access memory of the free-running CPU which thereafter can control transfer of additional executable code or load a permanent boot sequence into bulk erase (nonvolatile) flash memory. The invention can be incorporated into a wireless modem/packet terminal node controller. The input device may be a coupling to an external computer system, typically a serial input.

Programmable preamplifier unit with serial interface for disk data storage device using MR heads

Abstract: A disk drive preamplifier unit includes a serial interface circuit for receiving serially formatted control signals from an associated disk drive controller. The control signals contain several types of information, including head select, write current magnitude, bias for MR transducers, gain magnitude for a variable gain amplifier, and test and mode information. The preamplifier unit incorporates several test circuits in addition to the usual write unsafe detector circuit, and a multiplexer controlled by the mode control signals from the serial interface unit is used to select which test circuit or detector is coupled to a common test output terminal whose signals are coupled back to the controller for further processing. The preamplifier can be used to remotely test the head population of the head disk assembly, to measure the MR bias current through any of the MR transducers and to signal the controller in response to polling characters when a match is obtained between a character and preestablished multi-bit parameter information fixed in the preamplifier unit. A write current generator is shared by the write transducers and the MR bias test circuit, with a current scaling unit used to provide different current ranges from the common source. The preamplifier unit affords remote control and testing which can be adapted to evolving systems using firmware changes alone.

Distributed storage array system having a plurality of modular control units

Abstract: A RAID-compatible data storage system which allows incremental increases in storage capacity at a cost that is proportional to the increase in capacity. The system does not require changes to the host system. The control and interface functions previously performed by a single (or redundant) central data storage device controller are distributed among a number of modular control units (MCUs). Each MCU is preferably physically coupled to a data storage device to form a basic, low-cost integrated storage node. One of two bus ports interfaces an MCU with the host computer on a host bus, and the other bus port interfaces an MCU with one or more data storage devices coupled to the MCU by a data storage device bus. The serial interface ports provide a means by which each of the MCUs may communicate with each other MCU to facilitate the implementation of a memory array architecture. The entire data storage array may appear as a single device capable of responding to a single identification number on the host bus, or may appear as a number of independent devices. A controlling MCU receives a command and notifies the other MCUs that are involved in a read or write operation. Control of the host bus is transferred from one MCU to the next MCU in sequence so that the data is received by the host computer, or written to each data storage device, in the proper order.

System for enabling decoding of bar code and other symbols with a digital microcomputer connected via the input/output port thereof to the scanner

Abstract: A scanner communicates with a microcomputer over a serial communications link utilizing the serial I/O port of the microcomputer. Both signals representing the data which is scanned and signals representing commands to the scanner and commands from the scanner indicative of the status thereof (e.g., scanner trigger actuation) are communicated over a plurality of lines in the communication link. These lines may be of the type utilized for transmission of data and commands in accordance with a communications protocol, such as the RS-232 protocol. Interrupts are generated when the scanner is connected to the serial port via the communication link and the microcomputer is available for decoding. Then appropriate interrupts are generated to actuate the scanner and to respond to the data. The scanner may be a laser or optical beam scanner or a wand which is moved across a bar code symbol. The symbol has bars which are relatively opaque and reflective (black or white). The microcomputer translates the data which represents the width of each bar and the number of bars and the detection of the end of a bar code symbol (Quiet Zone) into digital values which are stored in memory and presented for decoding in accordance with programming of the microcomputer which decodes the symbol. The decoded symbol may be displayed graphically, with its opaque and reflective bars and the alphanumerics which the symbol represents, on the screen of a terminal including the microcomputer.

Remote display monitor system

Abstract: A monitor is remotely coupled to a source of display data for real-time display of the data thereon. The display is real-time in that the received data is converted to pixel values and is displayed by the remote monitor almost instantaneously except for some minor data hand-off and transmission delays. The remote monitor can be any kind of conventional text and/or graphics display device, e.g. a cathode ray tube device, but preferably is a flat panel, digital display. Preferably the system couples to a pre-existing data bus, e.g. an ISA, EISA, VLB or PCI bus, and an interface circuit communicates with the source of the display information, such as a processor on the bus. Digital pixel values are stored in a local frame buffer. A transmit controller transmits the stored pixel values over a preferably serial, optical transmission medium, to a remote circuit which stores them in a remote frame buffer. A remote processor controls the communication of pixel values from the remote frame buffer to the remote monitor. In some embodiments, the remote processor has data ports, e.g. a keyboard, pointing device and/or a serial port, and can be used to process operator inputs to perform functions such as pan and zoom on the display data. Also data input at the remote monitor can be sent back to the bus interface circuit via a second transmission medium, preferably optical and serial.

Interface between programmable electronically commutated motor and personal computer and method of operation

Abstract: A microcontroller with external memory interacts with a host computer or terminal via a fully isolated RS232 serial interface. An eight-bit D/A converter transforms signals generated digitally in the microcontroller. The low level analog signal at the D/A output is further amplified in a power amplifier which supplies a signal to the motor terminals of the motor to be programmed via solid state relays. The solid state relays form an array of switches which are selectively closed by a low level digit signal generated by the microcontroller and processed by digital circuits. Four signals may be modulated with a signal representing the line frequency and are used specifically in an emulation mode. The interface receives multi-function feedback signals (RPM) from the motor such as speed, memory, content, and diagnostic information. Comparators provide an integrity check of the connections (cable) and the input section of the motor (optocouplers). The comparators compare voltages and currents of a selected motor signal against pre-defined threshold levels.

Controlling synchronous serial access to a multiport memory

Abstract: An integrated circuit multiport memory supports synchronous access through a serial port In operation, a multiport memory of the present invention is coupled to a free running clock signal and a clock enable signal for internally synchronizing serial access The external clock enable signal prevents incrementing the sequence of serial access when serial access is interrupted In a synchronous memory of the present invention, the write data signal need not be held after the active edge of the serial clock, since serial data hold time is made independent of serial access memory write timing parameters When serial data signals are conveyed on a bidirectional line of a asynchronous serial data port of the present invention, a direction control circuit of the present invention is responsive to transfer and write enable signals and independent of the conventional serial output enable signal

Method and system for communicating between a plurality of semiconductor devices

Abstract: Serial high speed interconnect devices are integrated with semiconductor devices for simple and reliable communications and control between a plurality of semiconductor devices. The serial high speed interconnect devices transfer the data serially at a rate fast enough to replace large parallel data and address buses that require one conductive path per bit of data. Eliminating large parallel data and address buses allows the integrated circuit containing the semiconductor device to be smaller, simpler and lower in cost. The subsequent reduction in the size of the integrated circuits improves the layout density of electronic systems and reduces crosstalk and other undesirable signal transfer anomalies. The serial high speed interconnection devices are implemented with a low cost serial interface circuit technology that may be easily implemented on a semiconductor die in conjunction with the main circuits.

System architecture for processing and transporting page-map or bit-map data to a raster print engine

Abstract: A digital high-speed printing system architecture for processing contiguous raster-image data blocks for transmission to a marking engine, comprises a central processing unit ("CPU") and at least one video RAM device. Each video RAM device includes a dynamic band RAM, a serial access memory, a random access port for transmitting and receiving image data blocks to and from the dynamic band RAM, and a serial port for transmitting and receiving image data blocks to and from the serial access memory. The video RAM devices perform bi-directional image data block transfers between the dynamic band RAM and the serial access memory. Furthermore, the video RAM devices transfer image data blocks to and from the serial access port, and simultaneously transfer of image data blocks to and from the random access port. A CPU data bus is coupled between the CPU and the random access port for providing CPU access to the dynamic band RAM, such that the CPU can perform mapping operations on the image data blocks in dynamic band RAM. A dispatch FIFO is coupled to the marking engine; and serial bus is connected between the dispatch FIFO and the serial port, such that image data blocks can be dispatched from the serial access memory to the marking engines over the serial bus. Therefore, the system architecture allows for the dispatching of image data blocks from the serial access memory to be performed simultaneously to the mapping of image data blocks in dynamic band RAM.

Method and apparatus for providing a serial interface between an asynchronous transfer mode (ATM) layer and a physical (PHY) layer

Abstract: An extender circuit provides a serial communication interface between an ATM layer and a PHY layer. The extender circuit includes a first circuit serially coupled to a second circuit. The first circuit communicates in parallel with the ATM layer, and the second circuit communicates in parallel with the PHY layer. The extender circuit additionally includes a serial link which serially transmits signals between the first and second circuits. The serial link includes a first serial link for transmitting a first serial signal from the first circuit to the second circuit, and a second serial link transmitting a second serial signal from the second circuit to the first circuit. The first circuit and the second circuit include similar architecture. The first circuit includes a parallel interface circuit for communicating in parallel with the ATM layer and a serial interface circuit coupled to the parallel interface circuit for serially communicating with the second circuit. The parallel interface circuit includes control circuitry, such as a programmable logic device, and memory circuitry, such as a first-in-first-out (FIFO) memory device. The serial interface circuit includes serializing/deserializing circuitry which includes serializing circuitry for serializing a plurality of parallel signals received from the parallel interface circuit and outputting a plurality of serial output signals. The serializing/deserializing circuitry further includes deserializing circuitry for deserializing a plurality of serial input signals to form a plurality of deserialized signals and providing the deserialized signals to the parallel interface circuit.

Reprogrammable controller containing multiple programs

Abstract: A controller has a microcomputer, an electrically erasable and programmable memory which has a control program (CONTROL), a read only memory and a serial interface. A serial data transmission line can be connected to the serial interface. A program (PROG) for reprogramming the electrically erasable and programmable memory is stored in the read only memory. For reprogramming the electrically erasable and programmable memory, the controller receives the data, which are to be programmed, via the serial data transmission line from an external communications apparatus.

Power and data interface for peripheral devices

Abstract: An interface (12) is disclosed for coupling a peripheral device (18) to the serial port (14) of a computer (16). in one application, the interface allows the serial port to provide the power required by a scanner for operation. To reduce power consumption, the scanner is typically operated in either/a reduced-power, nonscanning mode or a higher power scanning mode. The interface may include an energy storage device (36) for storing energy from the serial port when the scanner is operated in the nonscanning mode and providing energy to the scanner when it is operated in the scanning mode. Thus, a scanner that requires more power than the serial port can provide at any one time can be used. The interface also includes a shutdown circuit (46) that prevents the scanner from being operated in conditions that might lead to the erroneous interpretation of data. Further, an input leakage isolation circuit (48) is included to prevent the discharge of the storage device when the scanner is not in use.

Integrated circuit with a serial port having only one pin

Abstract: A host adapter integrated circuit that contains data transfer modules has a serial port that uses a single serial port pin to communicate with a slave serial port input-output integrated circuit that interfaces to various resources that are included in a support circuit. The serial port forms a packet from each byte of information to be transferred from a module to the slave device by adding a start bit before the byte, followed by a parity bit at the end of the byte and followed by a stop bit. After transmitting the packet, the serial port waits for an acknowledge packet from the slave serial port input-output integrated circuit, for example for two clock cycles after transmission of the packet. For synchronous operation, a common oscillator drives the clock signal on the slave serial port input-output integrated circuit and host adapter integrated circuit. The serial port pin in the host adapter integrated circuit is connected to a shifter circuit in the serial port that serially clocks data from the serial port pin and passes the data parallelly to a bus in the host adapter integrated circuit and vice versa.

Serial interface having control circuits for enabling or disabling N-channel or P-channel transistors to allow for operation in two different transfer modes

Abstract: A serial interface includes a first port capable of transmitting and receiving data in a serial fashion. A first p-channel transistor is coupled to the a first port. A first n-channel transistor is coupled to the a first port. A first control circuit is coupled to the first p-channel transistor for disabling the first p-channel transistor so that the first port can operate in a first serial data transfer mode wherein the first n-channel transistor operates in an open-drain fashion. A second port is capable of transmitting and receiving a clock signal which is used to control data transfer through the first port. A second p-channel transistor is coupled to the a second port. A second n-channel transistor is coupled to the a second port. A second control circuit is coupled to the second p-channel transistor for disabling the second p-channel transistor so that the second port can operate in the first serial data transfer mode wherein the second n-channel transistor operates in an open-drain fashion.

Video game apparatus with external memory devices

Abstract: In a video reproducing apparatus such as a video game, operating devices and recording devices are connected with a simple structure to record game information while operating the game, and a plurality of small capacity of external secondary memory means can be used as a large capacity of external secondary memory means. The main body of the video game machine is connected to a plurality of the operating devices with a serial interface so that serial data is communicated bidirectionally in accordance with a predetermined communication procedure while at the same time connecting recording devices to the serial interface respectively corresponding to a plurality of operating devices to allow the main body of the game machine to write predetermined data into and read it from recording devices in accordance with a communication procedure. Moreover, the communication controller connected to the main bus to which the central processing unit of the main body of the machine is connected and a plurality of card connectors namely card slots where memory cards connected to the main bus via the communication controller are attached to or detached from freely are provided, and each card slot is independently controlled by the central processing unit via the communication controller to control the writing and/or reading of data extending over the plurality of external secondary memory means.

Method and system for reducing the number of connections between a plurality of semiconductor devices

Abstract: Serial high speed interconnect devices are integrated with semiconductor devices to reduce the number of input-output pins required for communications and control between a plurality of semiconductor devices. The serial high speed interconnect devices transfer the data serially at a rate fast enough to replace large parallel data and address buses that require one conductive path per bit of data. Eliminating large parallel data and address buses allows the integrated circuit assembly containing the semiconductor device to be smaller, simpler and lower in cost. The subsequent reduction in the size of the integrated circuits improves the layout density of electronic systems and reduces crosstalk and other undesirable signal transfer anomalies. The serial high speed interconnection devices are implemented with a low cost serial interface logic technology that may be easily implemented on a semiconductor die in conjunction with the main logic circuits.

System and method for sensing color and preventing use of unauthorized color formulation software

Abstract: A system and a method for preventing use of unauthorized software contained at a remote location which is to be used with a device having stored information is disclosed. The device includes firmware having a hash code, and a hash function for operating on an initiation string. The device has a communication interface. A remote storage location has an initiation string. The communication interface of the device and the remote storage location are interconnected for transferring information such as the initiation string between the device and remote storage location. The result of the hash function operation on the initiation string is compared with the hash code. The communication interface is enabled when the result of the hash function operation on the initiation string and hash code contained in the firmware are the same. In the illustrated embodiment, the device is a color sensor having a sensor body. The sensor senses and stores information about the color of a selected object such as on an automobile. A serial port on the sensor body is operatively associated with the color sensor and allows interconnection to a serial port of a remote computer. The remote computer receives stored color information from the sensor. The remote computer generates the initiation string to the sensor. The serial port is enabled when the result of the hash function on the initiation string and hash code are the same.