Showing papers on "Snapback published in 2023"
TL;DR: In this paper , the controllability of the three-layer snapback networks is investigated in the context of linear time-invariant linear time invariant (LTI) systems.
Abstract: This article studies the controllability of multi-input/multioutput linear time-invariant (LTI) systems in a snapback interlayer coupling framework. Several necessary and sufficient conditions for the controllability of the three-layer snapback networks are established. In addition, controllability conditions about the superposition of the three-layer networks are obtained. These conditions are related to smaller scale factor networks, showing the effects of the interlayer coupling frameworks, intralayer network topologies, node dynamics, inner interactions, and external control inputs on the controllability of the snapback networks. Moreover, controllability conditions of the three-layer snapback networks are extended to the $M$
01 Jan 2023
TL;DR: In this article , the features and physics of snapback involved in 2D NMOS structures having body/substrate contact at bottom and adjacent to source under the application of high current ramp at drain and zero gate voltage.
Abstract: This paper compares the features and physics of snapback involved in 2D NMOS structures having body/substrate contact at bottom and adjacent to source under the application of high current ramp at drain and zero gate voltage. We analyzes the S-shaped current–voltage characteristics of two structures for understanding the snapback phenomenon and operational window of compact memory devices. This work also evaluates the carrier electrostatics involving the electron–hole carrier build up and ambipolar current flow in the body of the structures. We also investigate the formation of memory cell in the body of NMOS under zero gate bias and ramp of high current stress at drain terminal due to bipolar turn.
TL;DR: In this article , a novel snapback-free superjunction reverse-conducting insulated gate bipolar transistor (SJ-RC-IGBT) is proposed and verified by simulation.
Abstract: A novel snapback-free superjunction reverse-conducting insulated gate bipolar transistor (SJ-RC-IGBT) is proposed and verified by simulation. In the SJ-RC-IGBT, the parasitic P/N/P/N structure as thyristor or Shockley diode demonstrates large conductivity due to an overabundance of carriers for reverse conduction. By preventing electrons from leaking across the N+ region at the collector side, the extra electron-blocking (EB) layer introduced in the SJ-RC-IGBT can dramatically enhance electron–hole pairs in the N/P-pillars. Hence, the SJ-RC-IGBT demonstrates a low on-state voltage (Von). In addition, snapback-free characteristics and a large safe operating area (SOA) are also achieved in the SJ-RC-IGBT. During the turn-off process, a significant amount of electrons are extracted by parasitic MOS across the EB layer at the collector side to decrease the turn-off loss (Eoff). According to the optimized results, the SJ-RC-IGBT with EB layer obtains an ultralow Eoff of 3.9 mJ/cm2 at Von = 1.38 V with 88% and 81% decreases, respectively, compared with the conventional reverse-conducting IGBT (CRC-IGBT) and superjunction IGBT (SJ-IGBT).
01 Mar 2023
TL;DR: In this paper , an extreme large snapback voltage as an alternate way to improve the ESD robustness is proposed for the RESURF LDMOS devices which usually have low failure threshold.
Abstract: Extremely large snapback voltage as an alternate way to improve the ESD robustness is proposed for the RESURF LDMOS devices which usually have low failure threshold. V t1 >> V BD is a “fail-to-protect” condition of the device which enables ESD protection to high-voltage power pins, expanding the ESD protection window for I/O applications. RESURF-implants in LDMOS result in lower I t1 , which is favorable for I/O devices with lower leakage. The effect of different LDMOS design approaches, load lines, and ESD stress duration on the V t1 is systematically evaluated, using TLP experiments and 3D TCAD simulations. Finally, device design engineering guidelines are presented to achieve large V t1 , while developing physical insights into the underlying mechanisms.
TL;DR: In this paper , double pocket implantation successfully suppresses the hole current crowding and also achieves higher SNBV for two-finger MOSFETs with different source/drain configurations.
Abstract: The snapback breakdown behavior of multi-finger MOSFETs was investigated using a device simulation. It is shown that snapback breakdown voltage (SNBV) varies depending on the source/drain configuration, even with the same two-finger structure. This results from the hole current crowding below the shared source, which further increases forward biasing at the source-substrate junction and eventually leads to premature activation of the parasitic bipolar junction transistor (BJT). Double-pocket implantation successfully suppresses the hole current crowding and also achieves higher SNBV for two-finger MOSFET.
28 May 2023
TL;DR: In this article , a novel snapback-free SOI LIGBT with Field Plate Resistances (FPR) is proposed and experimentally investigated, which not only effectively increases the anode distributed resistance to eliminate the snapback effect in the on-state, but also provides an electron extraction path during the turn off period to accelerate the turning off and decrease the turnoff loss.
Abstract: A novel snapback-free SOI LIGBT with Field Plate Resistances (FPR) is proposed and experimentally investigated. The FPR consisting of multiple polysilicon resistances is located above the field oxide at the anode side, which is compatible with the planar poly gate design. The two sides of FPR are connected with the P+ anode and N+ anode, respectively. The FPR not only effectively increases the anode distributed resistance to eliminate the snapback effect in the on-state, but also provides an electron extraction path during the turnoff period to accelerate the turning off and decrease the turnoff loss ( $E_{\text{off}}$ ). A 439V FPR SOI LIGBT is fabricated and decreases the $E_{\text{off}}$ by 36% at the expense of 7% increasement in on-state voltage drop ( $V_{\text{on}}$ ) compared with the conventional SOI LIGBT. The experimental results show that the proposed FPR SOI LIGBT could achieve a good tradeoff relationship between the $E_{\text{off}}$ and $V_{\text{on}}$ .
TL;DR: In this article , the impact of the anode contact in SBDs, PiN, JBS and MPS diodes is analyzed through TCAD simulations, and it is found that the splitting of the contact and an accurate selection of the Schottky barrier height on pzone is necessary to allow the onset of the bipolar conduction in MPS devices.
Abstract: In this paper, the impact of the anode contact in SBDs, PiN, JBS and MPS diodes is analyzed through TCAD simulations. The focus of the investigation is the correct simulation of the Schottky barrier height on the different areas of the device to correctly simulate a JBS or MPS structure. It is found that the splitting of the anode contact and an accurate selection of the Schottky barrier height on pzone is necessary to allow the onset of the bipolar conduction in MPS devices. In this way, it is possible to correctly analyze the behavior of an MPS diode, including the snapback phenomenon.
05 May 2023
TL;DR: The physical mechanism of the off-state avalanche breakdown process of SiC MOSFET which is composed of the active region and the termination region is analyzed by Sentaurus simulation and verified with TLP measurement data as mentioned in this paper .
Abstract: The physical mechanism of the off-state avalanche breakdown process of SiC MOSFET which is composed of the active region and the termination region is analyzed by Sentaurus simulation and verified with TLP measurement data. At different stages of off-state, the current components of the active region and the termination region of SiC MOSFET are different, and a detailed explanation is given. The leakage current is generated by the presence of high impact ionization coefficients in the PN Junction of the transition region before the occurrence of the snapback. When the snapback occurs, electrons accumulate in the n-drift/n-substrate, while the previously generated large number of holes lowers the potential barrier of the n+-source/p-body to 0.13eV to form punch through current. The parasitic NPN bipolar transistor is not considered to be triggered for no continuous hole current injects into p-body. The termination region structure determined the avalanche breakdown voltage, and the active region decides the snapback current. TLP avalanche breakdown measurement indicates that the fabricated SiC MOSFETs with the same structure parameter as that utilized in the simulation shows the snapback phenomena, which verified the validity of the physical mechanism analysis of the off-state avalanche breakdown process.
01 Jan 2023
TL;DR: In this article , the authors modeled the history effect of floating-body SOI-MOSFETs in HiSIM_SOI, an industry standard compact model for SOI.
Abstract: In course of device scaling toward the usage of thinner semiconductor layer, body-tied SOI-MOSFETs have exhibited the onset of floating-body-like effects commonly known to floating-body SOI-MOSFETs. One of such manifestations is a hump or sudden jump in drain-to-source and body currents notably in the subthreshold bias region. This discontinuous behavior is attributed to the onset of snapback through 3D device simulation enabling a realistic placement of the body contact. Thinner SOI layer easily depletes and the consequent vanishment of neutral region hinders impact ionization-generated holes from exiting the SOI layer at the body contact, thus causing a buildup of body potential and an enhancement of carrier injection at the source/body junction. These physical insights were modeled in HiSIM_SOI, an industry-standard compact model for SOI-MOSFETs. Thanks to the slowness of its physical mechanism in comparison to device operating speed in actual circuitry, the time-dependent floating-body effect, also known as the history effect, would be mitigated.