Showing papers on "Spy-Bi-Wire published in 2006"

Optimized jtag interface

Abstract: An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

JTAG to system bus interface for accessing embedded analysis instruments

Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, mechanisms, and means for providing a JTAG to system bus interface for accessing embedded analysis system(s). JTAG commands are received and converted into commands sent out a bus to a device including an embedded analysis instrument, with results received over the bus forwarded out the JTAG interface to an external device. Such a JTAG to system bus interface may eliminate the need to provide separate JTAG TAP interfaces on each ASIC of a board, and/or eliminate the need to daisy chain multiple TAP interfaces of multiple ASICs in order to provide a single TAP interface for accessing the multiple embedded testing instruments.

Controller receiving combined TMS/TDI and suppyling separate TMS and TDI

Abstract: An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

Reusable, Low-cost, and Flexible Multidrop System JTAG Architecture

Abstract: A reusable, low-cost, and flexible multidrop system JTAG1 architecture has been developed at Brocade as an alternative to more expensive commercial solutions. This architecture allows JTAG operations to be driven by a local on-board processor or an external host. An add-drop network design allows all on-board JTAG devices to be grouped into several smaller chains and enables the chains to be combined flexibly for various JTAG operations. By implementing this architecture in a low-cost Complex Programmable Logic Device (CPLD), it has been used in stand-alone single-board systems as well as complex multiboard chassis systems at Brocade.

PXI Express Based JTAG / Boundary Scan ATE for Structural Board and System Test

Abstract: Being well established as a valuable test and debug access methodology in the commercial electronics business, JTAG/ boundary scan as defined in IEEE Std. 1149.1 continues to advance into government and military applications as well. This test technology can be implemented in test systems based on various hardware platforms. This paper presents benefits a high speed tester platform such as PXI express provides for structural test and in-system programming applications based on JTAG / boundary scan access.

A Novel On-chip Debug System with Quick All-registers Scan Chain Based on JTAG

Abstract: JTAG defines a serial interface to access test-dedicated logic embedded in integrated circuits. As an extension, a test platform based on JTAG standard can support general verifications and debug functions for SOC. The paper presents an on-chip debug system based on JTAG standard for embedded microprocessors. It provides powerful functions for the system. For example, hardware breakpoints, single step execution mode, monitoring the registers, programming. An all-registers structure is used to support quick all-registers monitoring functions. Moreover, the paper contributes to the research of no-gap transfer of debug functions

Design of PCI-1149.1 Boundary-scan Master Controller

Abstract: JTAG master unit is a very important circuit in the boundary-scan test environment. In this paper, we design a PCI-1149.1 Boundary-Scan Master Controller. We not only design a JTAG master core based on the finite state machine, but also employ First-In-First-Out (FIFO) technique in the master core to improve the test speed of boundary-scan. After simulated with MAX+PLUS II, the core is successfully integrated in a FPGA and used in a PCI-1149.1 controller now. Experiment results prove our JTAG master core and PCI-1149.1 Boundary-Scan Master Controller are correct.