Showing papers on "Synchronizer published in 1979"

The Anomalous Behavior of Flip-Flops in Synchronizer Circuits

Abstract: Quantitative results of the observations of oscillatory and metastable behavior of common flip-flops in response to logically undefined input conditions, such as those that occur in synchronizers and arbiters, are presented. The results are obtained with the help of a circuit developed for this purpose which measures the failure rate for a certain flip-flop and frequency. It is found that the obtained results are in good correlation with observed failure rates of a synchronizer with both short and long flip-flop resolution times allowed.

Single shift rail manual transmission with overdrive speed ratio

Abstract: A multiple ratio manual power transmission mechanism for an automotive vehicle comprising main torque delivery gears (52. 58, 62 and 68) and a cluster gear assembly (82) having gear elements engageable with each of the main torque delivery gears, a pair of double acting synchronizer clutch mechanisms (98 and 170) for selectively actuating four of said main torque delivery gears to establish two underdrive ratios, a direct-drive ratio and an overdrive ratio, and a single shift rail (214) and shift lever assembly (250) for actuating said synchronizer clutch mechanisms (98 and 170) including a first motion reversing lever assembly (204) establishing a connection between the single shift rail (214) and the synchronizer clutch mechanism (170) for third and fourth ratio changes and another lever assembly (134) for reversing the motion imparted to a reverse drive pinion (104) by the single shift rail (214). the reverse drive pinion (104) being shiftable to a driving position or to an inoperative position and the synchronizer clutch mechanism (98) for the first and second speed ratio changes including an integral main drive gear (96) that forms a part of the reverse torque delivery path.

Bit synchronizer with early and late gating

Abstract: This device generates clock pulses which are synchronized with the bit data rate of an input antipodal bit pattern. The device can be used with multiple input data channels whenever such channels are synchronized, i.e., the periodicity of each channel is the same and the phase relationship between channels is fixed. For example, it can be used with QPSK modulation with two input basebands; or with biphase shift keying, frequency shift keying, or other types of modulation with only one baseband input. The circuit uses a form of delay lock loop which estimates the mean zero crossing instant of the input data stream. It compares the zero crossings with early and late gates which are generated on the basis of prior analysis of the input stream. A multiple transition detector circuit is employed when the operating environment is very noisy to inhibit the counting of multiple zero crossings during a combined early gate/late gate period.

Comments on "A Note on Synchronizer or Interlock Maloperation"

Abstract: E. G. Wormald's note1proposes a way to prevent metastable action in synchronizers. Experimental results from testing his suggested circuits show that his solution does not work. A reference to a general proof that synchronizers must have a region of metastable action is given.

Frame synchronizer having a write-inhibit circuit

Abstract: A frame synchronizer for a television receiver in which the incoming television signal is digitized and stored in a memory, includes a circuit for generating a write-inhibit control signal for inhibiting the write-in of a digitized second television signal into the memory between the switchover from a first television signal to the second television signal and the beginning of a complete frame of the second television signal.

Characterization and Scaling of MOS Flip Flop Performance in Synchronizer Applications

Abstract: The measured and calculated values of t he Flip Flop parameters needed to specify synchronizer reliability are presented for 3 different depletion-load, silicon gate, NMOS, R-S Flip Flop circuits with gate lengths ranging from 6μm to 4.2μm. Estimates of the probability of synchronizer failure to resolve within allowed or desired times can be determined from these parameters.

Symbols communication system

Abstract: A data communications system for transmitting and receiving 64 different audio-frequency signals representing 64 respective alpha-numeric code symbols. A synchronizing signal consists of three time-spaced bursts where each burst consists of three audio-frequency signals. A following information signal consists of a three time-spaced message bursts where each burst consists of twenty audio-frequency signals, all three of the message bursts containing the same audio-frequency signals but in different orders. A receiver includes synchronizer means to recognize the predetermined synchronizing signal, and decoder means enabled and synchronized by the synchronizer means to decode the information signal. The audio-frequency signals may be 64 different fixed-frequency tones, or may be 64 differently-changing signals such as may be produced by unidirectional phase shift keying by 64 different pseudo-random number codes.

Symbol synchronization in convolutionally coded systems (Corresp.)

Abstract: Alternate symbol inversion is sometimes applied to the output of convolutional encoders to guarantee sufficient richness of symbol transition for the receiver symbol synchronizer. A bound is given for the length of the transition-free symbol stream in such systems, and those convolutional codes are characterized in which arbitrarily long transition free runs occur.

Synchronizer ring for transmission synchromesh device

Abstract: A synchronizer ring for a synchromesh device for use in a transmission comprises an annular body of a wear-resistant metal forming a conical slide surface, and a main ring body made of a resin molded integrally on the annular body. The synchronizer ring according to the invention is light weight and economical of manufacture and can perform smooth contacts at chamfered surfaces and operate without producing any noise.

Method of and system for synchronizing data reception and retransmission aboard communication satellite

Abstract: A receiver aboard a communication satellite, designed to detect digital signals arriving in intermittent bursts from a ground station with a bit cadence differing but slightly from a clock frequency f s generated by a time base on the satellite, comprises a synchronizer controlled by that time base for reorganizing the detected bits into a data frame in step with clock frequency f s preparatorily to processing and retransmission thereof. The synchronizer samples a square wave of frequency 2f s substantially at the midpoint of an initial bit period of an incoming signal stream, with the aid of a timing signal extracted from that signal stream, and determines from the sample whether this square wave or an inversion thereof is to be used in establishing the instants of reading of the subsequently received bits. The bits thus read, after interim storage in two cascaded registers, are fed to a data processor in the rhythm of clock frequency f s . No data are lost as long as the drift between the clock cycles and bit periods does not exceed one fourth of a clock cycle for the duration of a burst.

Lubricating oil inducing equipment of vehicleeused power transmission system

Abstract: PURPOSE:To lubricate oil effectively for the end of an axially supported countershaft of a vehicle-used power transmission system, a transmission gear assembled on the counter shaft, and an interrupter. CONSTITUTION:A counter shaft 33 is axially supported to turn freely on a boss 21 standing on the inwall of a casing housing a gear transmission system 30. The counter shaft 33 is geared with an output shaft 32 to which driving power of an engine not illustrated is transmitted. A transmission gear of a 5-shifting gear 33h is assembled to turn freely on the shaft 33. A synchronizer 33e for interrupting is splined in connection with the gear 33h. An oil reservoir 62 receiving lubricating oil scraped up by said transmission gear 37h is provided on the inwall of the casing upwards said boss 21c. The lubricating oil in the oil reservoir 62 is fed for the synchronizer 33e and the transmission gear 33h through oil passes 68a-68c.

Support for T. J. Chaney's Comments on "A Note on Synchronizer or Interlock Maloperation"

Abstract: Chaney's masterful exposition [1] on my suggestion [2] for defeating synchronizer or interlock maloperation should provide some much needed publicity for the nature and possible effects of synchronizer metastability. Hopefully, the discussion will discourage further attempts to eliminate this unavoidable characteristic.

Brushless synchronizer discharge resistance mounting device

Abstract: PURPOSE:To facilitate disassembly inspection with compact structure and improve the cooling effect in the fan effect generated by a support by changing a discharge resistor into ring-shaped or belt plate shaped ones and mounting it to a rotary rectifier through the support.

Remote control system

Abstract: PURPOSE:To make small the capacity of exclusive control channel by transmitting the control information via the communication channel through the allocation of one of the communication channels in the time frame information for the exclusive control channel during the transfer of control information CONSTITUTION:The master station 1, remote line concentration unit 2, and dispersion type line concentrators 12-0 to 12-l are connected with the transmission line 6 The master station 1 consists of the highway switch 3, master station controller 4, master station synchronizer 5, and the signal processor 19, and the remote line concentrator 2 comprises the line concentrator 7, remote line concentration controller 8, remote synchronizer 9, subscriber circuits 10-0 to 10-k and 11-0 to 11-k, and the dispersion type line concentrator 12 is made up of the remote terminal RT, subscriber circuit and subscribers

Color synchronizer of beam index type picture receiver

Abstract: PURPOSE:To attain stable color synchronization with invariably-definite gate operation, by counting an index signal before a process and by starting a divider circuit with a reset pulse obtained through the counting. CONSTITUTION:Sub-counter circuit 52 starts by reset pulse (G) from multivibrator 51 to count an index signal, the output of amplitude limiter circuit 46, thereby generating reset pulse (G'') which allows 1/3 divider circuit 48 to start. Even if the timing of pulse (G'') varies with the phase of the input signal of circuit 52, the phase of input signal 4(fi)D[fi; index frequency] of circuit 48 since depending upon the input signal of index-signal processing circuit 47 varies in the same direction, so that the start will not become out of timing. The accuracy of pulse (G) allowing circuit 52 to start is Tb'=1/fi=140m sec., which provides room four times as much as cnoventional one, so that stable synchronization can be attained.

Automatic control system for frame synchronizer

Abstract: PURPOSE:To eliminate occurrence of the screen shock completely by adding the pilot singal showing the VTR output to the VTR output and thus securing an automatic switching to the operation mode instantaneously for the input signal. CONSTITUTION:The band corresponding to pilot signal p is eliminated for the signal given from VTR1 through band eliminating filter 2. Then at pilot signal generator 3, the signal is mixed with the VTR output through mixer 4 which generated the fixed frequency of, for example, 4.5MHz, and the output is supplied to switch 5. While the output of camera 6 featuring the stable time axis unlike the VTR output is supplied concurrently to switch 5. The both output are then switched and delivered to be transmitted to base station 8 through microwave repeating installation 7. And pilot signal receiver 10 at station 8 detects presence or absence of signal p to send both the mode switch signal and the writing inhibition control signal to frame synchronizer FS11. At the same time, TBC adaptor 9 transmits the synchronous signal, the video signal and the clock pulse to FS11 when the VTR signal is coming in.

Frame phase synchronizer

Abstract: PURPOSE:To attain the improvement of speech quality and a decrease in error rate by arranging shift registers for the write control of input PCM signals and by allowing them to be an elastic storage and series-parallel converter circuit. CONSTITUTION:Frame synchronous circuit 18 detects the frame synchronizing position of a time-division multiple PCM signal, shift registers 20 23 are provided which has a number of bits equivalent to the word length of the signal, and the phase of a write clock to registers 20 23 is compared 23 with that of a switching signal sequentially changing over paralleled outputs of registers 20 23. Corresponding to its result, it is decided through write control 19 whether a word of fixed codes in the PCM signal should be written to the 1st and 2nd registers at the same time and the following word should be written to the 3rd register or the following words should be written skipping over the word to be written to the 1st register. Namely, registers 20 22 are used as both an elastic storage and series-parallel converter, thereby realizing the improvement of speech quality and a decrease in error rate.

Processor for analog signal

Abstract: PURPOSE:To shorten a signal read-out time to a CPU, etc, by providing an address change-over circuit which changes over address signals from a synchronizer CONSTITUTION:Analog signals from analog signal supply 1 are indicated by the address signal of synchronizer 7 and then supplied to A-d converter 4 via analog switch 2 which is switched sequentially every constant time Through the instruction of synchronizer 7, A-D converter 4 converts analog signals into digital signals, which are stored in a place, indicated by the address signal of synchronizer 7, in digital memory 6 In order to read signals in CPU5 for the purpose of a signal process, a signal assigning the fixed address of memory 6 is transmitted from CPU5 This address signal arrives at memory 6 and the signal of analog signal source 1 is read out as a digital signal being delayed by the only operation time of memory 6, and processed

Design Aspects and Reliability of a Synchronizer Made in MOS Technology

Abstract: In asynchronous communication between digi¬ tal systems signals may occur that are not logically defined [l] . An example is a multimicroprocessor system of which the microprocessors do not share a common clock. This means that signals are generated random in time. Especially it can happen that an input signal is changing during a sample clock edge. This situation can cause a system failure. The usual treatment of this problem is to design a synchronizer (most commonly a flip-flop), which has to take care of reliable communi¬ cation between asynchronous subsystems.There¬ fore, the time a flip-flop needs to recover from a metastable state (Fig. la) must be as small as possible. Synchronizers have alrea¬ dy been the subject of some papers [l] [6] . This paper deals with the design aspects and reliability of a synchronizer made in MOStechnology. resistance of the loads and C the nodal capa¬ citance. The following considerations apply to a flipflop with enhancement transistors only. Tran¬ sistor T2 in Fig. 3 is in saturation, so (from the simple MOS formula):

Intraaoffice phase synchronizer

Abstract: PURPOSE:To improve reliability and mounting density with a circuit scaled down, by generating a gate signal which covering the extent of dispersion in frame phase and by detecting the frame position within the extent. CONSTITUTION:Discrimination circuit 16 generates discriminatively PCM signal transmitted inside an office and bit-phase synchronization 17 of generated signals is done; and then, shift register 20 delays its output bit by bit and each bit output is selectively allowed to pass through AND gates 241 24M. Gate-signal generating circuit 22, on the other hand, generates a gate signal covering the extent of the dispersion in frame position between PCM signals of each circuit transmitted within the office, and during the interval of this gate signal, detection 21 of the frame- synchronizing code of the PCM signal is made, so that control circuit 23 will allow AND gates to open by selecting some of bit outputs of register 20 judging from the detection result. Consequently, the circuit can be scaled down and the improvement of reliability and mounting density can be attained.